Method of forming a micro LED device with self-aligned metallization stack

• US 9,548,332 B2
• Filed: 04/27/2012
• Issued: 01/17/2017
• Est. Priority Date: 04/27/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Hu, Hsin-Hua, Bibl, Andreas
• Primary Examiner(s): SAYADIAN, HRAYR
• Application Number:
  US13/458,932
• Publication Number:
  US 20130285086A1
• Time in Patent Office: 1,726 Days
• Field of Search: 257/98, 257/E33.06, 257/E33.066, 438/29, 438/34
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 2224/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating

Abstract

A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, a patterned sacrificial layer is utilized to form a self-aligned metallization stack and is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes.

Claims

1. A method of forming a micro LED array comprising:

forming a plurality of laterally separate self-aligned metallization stacks within a corresponding plurality of openings in a patterned sacrificial layer formed on a p-n diode layer;

bonding a first substrate stack including the plurality of laterally separate self-aligned metallization stacks, the patterned sacrificial layer, and the p-n diode layer to a second substrate with a bonding layer;

etching through the p-n diode layer to form a plurality of micro p-n diodes over the plurality of separate metallization stacks, and exposing the patterned sacrificial layer laterally between the plurality of separate metallization stacks; and

removing the patterned sacrificial layer.

2. The method of claim 1, wherein forming the plurality of laterally separate self-aligned metallization stacks within the corresponding plurality of openings in the patterned sacrificial layer formed on the p-n diode layer comprises:

depositing a sacrificial layer over the p-n diode layer;

forming a patterned mask layer over the sacrificial layer, the patterned mask layer including the plurality of openings exposing the sacrificial layer;

selectively etching the sacrificial layer relative to the mask layer to remove the exposed sacrificial layer within the plurality of openings and to remove a portion of the sacrificial layer underneath the patterned mask layer;

depositing a metallization stack layer over the patterned mask layer and p-n diode layer;

lifting off the patterned mask layer to leave behind the plurality of metallization stacks and the patterned sacrificial layer over the p-n diode layer.

3. The method of claim 1, wherein etching through the p-n diode layer comprises plasma etching.

4. The method of claim 1, wherein the plurality of self-aligned metallization stacks include an electrode layer and a barrier layer.

5. The method of claim 4, wherein the barrier layer covers an elevated surface and sidewalls of the electrode layer.

6. The method of claim 5, wherein the electrode layer is reflective.

7. The method of claim 6, wherein the electrode layer comprises a material selected from the group consisting of silver and nickel.

8. The method of claim 5, wherein forming the plurality of laterally separate self-aligned metallization stacks comprises depositing the barrier layer at a higher power than the electrode layer, or at a lower pressure than the electrode layer.

9. The method of claim 1, wherein the patterned sacrificial layer is a non-metallic layer.

10. The method of claim 9, wherein the patterned sacrificial layer comprises SiO₂.

11. The method of claim 4, wherein the patterned sacrificial layer is thicker than the plurality of laterally separate self-aligned metallization stacks.

12. The method of claim 11, wherein the patterned sacrificial layer is approximately twice as thick as the plurality of laterally separate self-aligned metallization stacks.

13. The method of claim 4, wherein forming the plurality of self-aligned metallization stacks comprises a technique selected from the group consisting of evaporation and sputtering.

14. The method of claim 1, further comprising depositing a conformal dielectric barrier layer on side surfaces and a portion of a bottom surface of each of the plurality of micro p-n diodes.

15. The method of claim 1, wherein the bonding layer has a liquidus temperature of approximately 350°

C. or lower.

16. The method of claim 15, wherein the bonding layer has a liquidus temperature of approximately 200°

C. or lower.

17. The method of claim 15, wherein the bonding layer comprises indium.

18. The method of claim 15, wherein bonding the first substrate stack to the second substrate with the bonding layer comprises bonding a first bonding layer on the first substrate stack with a second bonding layer on the second substrate.

19. The method of claim 18, wherein bonding comprises alloy bonding or fusion bonding the first and second bonding layers.

20. A method of forming a micro LED array comprising:

depositing a sacrificial layer over a p-n diode layer; and

forming a patterned mask layer over the sacrificial layer, the patterned mask layer including a plurality of openings exposing the sacrificial layer;

forming a patterned sacrificial layer, wherein forming the patterned sacrificial layer includes selectively etching the sacrificial layer relative to the mask layer to remove the exposed sacrificial layer within the plurality of openings and to remove a portion of the sacrificial layer underneath the patterned mask layer;

depositing a metallization stack layer over the patterned mask layer and p-n diode layer;

lifting off the patterned mask layer to leave behind a plurality of metallization stacks and the patterned sacrificial layer over the p-n diode layer, wherein the patterned sacrificial layer is thicker than the plurality of metallization stacks;

bonding a first substrate stack including the plurality of metallization stacks, the patterned sacrificial layer and the p-n diode layer to a second substrate with a bonding layer;

plasma etching through the p-n diode layer to form a plurality of micro p-n diodes over the plurality of separate metallization stacks, and exposing the patterned sacrificial layer laterally between the plurality of separate metallization stacks; and

removing the patterned sacrificial layer.

21. A method of forming a micro LED array comprising:

depositing a sacrificial layer over a p-n diode layer formed on a growth substrate; and

forming a patterned mask layer over the sacrificial layer, the patterned mask layer including a plurality of openings exposing the sacrificial layer;

forming a patterned sacrificial layer, wherein forming the patterned sacrificial layer includes selectively etching the sacrificial layer relative to the mask layer to remove the exposed sacrificial layer within the plurality of openings and to remove a portion of the sacrificial layer underneath the patterned mask layer;

depositing a metallization stack layer over the patterned mask layer and p-n diode layer;

lifting off the patterned mask layer to leave behind a plurality of metallization stacks and the patterned sacrificial layer over the p-n diode layer, wherein the patterned sacrificial layer is thicker than the plurality of metallization stacks.

22. The method of claim 21, wherein the plurality of self-aligned metallization stacks each include an electrode layer and a barrier layer covering an elevated surface and sidewalls of the electrode layer.

23. The method of claim 22, wherein the electrode layer is reflective.

24. The method of claim 23, wherein the electrode layer comprises a material selected from the group consisting of silver and nickel.

25. The method of claim 22, wherein forming the plurality of laterally separate self-aligned metallization stacks comprises depositing the barrier layer at a higher power than the electrode layer, or at a lower pressure than the electrode layer.

26. The method of claim 22, further comprising:

bonding a first substrate stack including the plurality of metallization stacks, the p-n diode layer, and the growth substrate to a second substrate with a bonding layer; and

removing the growth substrate.