Semiconductor device and method of forming an inductor on polymer matrix composite substrate

• US 9,548,347 B2
• Filed: 05/28/2014
• Issued: 01/17/2017
• Est. Priority Date: 10/29/2005
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Lin, Yaojian
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US14/289,344
• Publication Number:
  US 20140264736A1
• Time in Patent Office: 965 Days
• Field of Search: 257528-538
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.

Claims

1. A semiconductor device, comprising:

a polymer matrix composite substrate;

a first insulating layer completely covering a surface of the polymer matrix composite substrate;

an inductor formed over the first insulating layer; and

an interconnect structure formed over the inductor and first insulating layer and configured to electrically and mechanically connect the semiconductor device to a second substrate.

2. The semiconductor device of claim 1, further including a capacitor formed over the polymer matrix composite substrate, the capacitor including,

a first conductive layer formed over the polymer matrix composite substrate;

a second insulating layer formed over the first conductive layer; and

a second conductive layer formed over the second insulating layer.

3. The semiconductor device of claim 2, further including a third insulating layer formed over the second insulating layer.

4. The semiconductor device of claim 1, further including a second insulating layer formed over the first insulating layer and inductor.

5. The semiconductor device of claim 1, wherein the interconnect structure includes a bump.

6. The semiconductor device of claim 1, further including a resistive layer formed over the polymer matrix composite substrate.

7. A semiconductor device, comprising:

a polymer matrix composite substrate;

a first insulating layer formed over the polymer matrix composite substrate;

an integrated passive device formed over the first insulating layer; and

an interconnect structure formed over the first insulating layer to couple the integrated passive device to a second substrate.

8. The semiconductor device of claim 7, wherein the integrated passive device includes an inductor.

9. The semiconductor device of claim 7, wherein the integrated passive device includes a capacitor comprising,

a first conductive layer formed over the polymer matrix composite substrate;

a second insulating layer formed over the first conductive layer; and

a second conductive layer formed over the second insulating layer.

10. The semiconductor device of claim 7, wherein the interconnect structure includes a bump.

11. The semiconductor device of claim 7, further including a resistive layer formed over the polymer matrix composite substrate.

12. The semiconductor device of claim 7, further including a second insulating layer formed over the first insulating layer and integrated passive device.

13. The semiconductor device of claim 7, wherein a coefficient of thermal expansion of the polymer matrix composite substrate matches a coefficient of thermal expansion of the integrated passive device.

14. A semiconductor device, comprising:

a polymer matrix composite substrate;

an integrated passive device formed over the polymer matrix composite substrate; and

an interconnect structure formed over the integrated passive device and configured to attach the semiconductor device to a second substrate.

15. The semiconductor device of claim 14, wherein the integrated passive device includes an inductor.

16. The semiconductor device of claim 14, wherein the integrated passive device includes a capacitor comprising,

a first conductive layer formed over the polymer matrix composite substrate;

an insulating layer formed over the first conductive layer; and

a second conductive layer formed over the insulating layer.

17. The semiconductor device of claim 14, wherein the interconnect structure includes a bump.

18. The semiconductor device of claim 14, further including a resistive layer formed over the polymer matrix composite substrate.

19. The semiconductor device of claim 14, further including:

a first insulating layer formed over the polymer matrix composite substrate; and

a second insulating layer formed over the first insulating layer and integrated passive device.

20. The semiconductor device of claim 14, wherein a coefficient of thermal expansion of the polymer matrix composite substrate matches a coefficient of thermal expansion of the integrated passive device.

21. A semiconductor device, comprising:

a polymer matrix composite substrate;

an integrated passive device formed over the polymer matrix composite substrate; and

an interconnect structure disposed over the integrated passive device to couple the integrated passive device to a second substrate.

22. The semiconductor device of claim 21, wherein the interconnect structure includes a bump.

23. The semiconductor device of claim 22, further including a printed circuit board, wherein the bump is bonded to the printed circuit board.

24. The semiconductor device of claim 21, wherein a coefficient of thermal expansion of the polymer matrix composite substrate matches a coefficient of thermal expansion of the integrated passive device.