High mobility devices with anti-punch through layers and methods of forming same

• US 9,548,362 B2
• Filed: 11/26/2014
• Issued: 01/17/2017
• Est. Priority Date: 10/10/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Fung, Ka-Hing, Wu, Zhiqiang
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US14/555,128
• Publication Number:
  US 20160104776A1
• Time in Patent Office: 783 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

An embodiment semiconductor device includes a fin extending upwards from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having APT dopants and a channel region over the APT layer. The channel region is substantially free of APT dopants. The semiconductor device further includes a conductive gate stack on a sidewall and a top surface of the channel region.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming an anti-punch through (APT) layer over a semiconductor substrate, wherein the APT layer comprises first APT dopants;

forming a semiconductor layer over the APT layer;

patterning the semiconductor layer and the APT layer to define;

a first fin extending upwards from the semiconductor substrate, wherein the first fin comprises a first APT layer portion and a first semiconductor layer portion over the first APT layer portion; and

a second fin comprising a second APT layer portion and a second semiconductor layer portion over the second APT layer portion;

implanting second APT dopants in the second APT layer portion after forming the second semiconductor layer portion, wherein the second APT dopants are of a different type than the first APT dopants; and

forming a conductive gate stack on a top surface and a sidewall of the first semiconductor layer portion of the first fin.

2. The method of claim 1, wherein the semiconductor layer is substantially free of any APT dopants.

3. The method of claim 1 further comprising:

prior to implanting the second APT dopants, removing the second semiconductor layer portion to expose a surface of the second APT layer portion substantially parallel to a major surface of the semiconductor substrate.

4. The method of claim 1 further comprising masking the first fin while implanting the second APT dopants.

5. The method of claim 1, wherein implanting the second APT dopants comprises implanting at least about twice as many of the second APT dopants as the first APT dopants in the second APT layer portion.

6. The method of claim 1, wherein the second APT layer portion comprises silicon boron phosphorous (SiBP) or silicon carbon boron phosphorous (SiCBP) after implanting the second APT dopants.

7. The method of claim 1, wherein forming the APT layer comprises epitaxially growing a layer comprising silicon boron or silicon carbon boron.

8. The method of claim 1 further comprising forming source and drain regions in the first fin adjacent the conductive gate stack, wherein the first APT layer portion is disposed under the source and drain regions.

9. A method comprising:

patterning first fin extending upwards from a substrate, wherein the first fin comprises;

a first anti-punch through (APT) portion comprising first APT dopants; and

a first semiconductor portion over the first APT portion;

patterning second fin extending upwards from a substrate, wherein the second fin comprises;

a second anti-punch through (APT) portion comprising second APT dopants of a same type as the first APT dopants; and

a second semiconductor portion over the second APT portion;

masking the first fin;

while masking the first fin, removing the second semiconductor portion to expose the second APT portion;

while masking the first fin, implanting third APT dopants of a different type than the second APT dopants into the second APT portion after removing the second semiconductor portion; and

after implanting the third APT dopants, forming a third semiconductor portion over the second APT portion.

10. The method of claim 9, wherein implanting third APT dopants comprises implanting at least twice as many third APT dopants as the second APT dopants.

11. The method of claim 9, wherein the first semiconductor portion is substantially free of APT dopants.

12. The method of claim 9, wherein the first APT dopants and the second APT dopants comprise silicon carbon boron or silicon boron.

13. The method of claim 12, wherein the first APT dopants and the second APT dopants comprise silicon carbon boron having an atomic concentration of carbon of about 0.5% to about 1%.

14. The method of claim 9, wherein the third APT dopants comprise phosphorous, and wherein after implanting the third APT dopants, the second APT portion comprises silicon carbon boron phosphorous or silicon boron phosphorous.

15. The method of claim 9, wherein patterning the first fin and patterning the second fin comprises:

forming an APT layer comprising the first APT dopants and the second APT dopants over a first semiconductor layer;

after forming the APT layer, forming a second semiconductor layer over the APT layer; and

patterning the APT layer and the second semiconductor layer to form a first fin and a second fin.

16. A method for forming a semiconductor device, the method comprising:

forming an anti-punch through (APT) layer over a semiconductor substrate, wherein the APT layer comprises first APT dopants;

forming a semiconductor layer over the APT layer;

patterning the semiconductor layer and the APT layer to define;

a first fin extending upwards from the semiconductor substrate, wherein the first fin comprises a first APT layer portion and a first semiconductor layer portion over the first APT layer portion; and

a second fin comprising a second APT layer portion and a second semiconductor layer portion over the second APT layer portion;

implanting second APT dopants in the second APT layer portion after forming the second semiconductor layer portion, wherein the second APT dopants are of a different type than the first APT dopants, and wherein a ratio of the second APT dopants in the second APT layer portion to the first APT dopants in the second APT layer portion is at least two to one; and

forming a conductive gate stack on a top surface and a sidewall of the first semiconductor layer portion of the first fin.

17. The method of claim 16, wherein a first semiconductor layer portion of the semiconductor layer over the first APT layer portion is substantially free of any APT dopants.

18. The method of claim 16 further comprising removing a second semiconductor layer portion of the semiconductor layer over the second APT layer portion to expose the second APT layer portion before implanting the second APT dopants in the second APT layer portion.

19. The method of claim 18 further comprising after implanting the second APT dopants in the second APT layer portion, forming an additional semiconductor layer over the second APT layer portion.

20. The method of claim 16 further comprising masking the first fin while implanting the second APT dopants in the second APT layer portion.