High power insulated gate bipolar transistors

• US 9,548,374 B2
• Filed: 04/24/2014
• Issued: 01/17/2017
• Est. Priority Date: 08/17/2006
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun, Ryu, Sei-Hyung, Jonas, Charlotte, Agarwal, Anant K.
• Primary Examiner(s): Dulka, John P
• Application Number:
  US14/260,717
• Publication Number:
  US 20150287805A1
• Time in Patent Office: 999 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

A method of forming a transistor device include forming a drift layer of a first conductivity type, forming a well of a second conductivity type in the drift layer, forming a JFET region with first conductivity type dopant ions in the drift layer, forming a channel adjustment layer of the first conductivity type on the JFET region and the well, implanting first conductivity type dopant ions to form an emitter region of the first conductivity type extending through the channel adjustment layer and into the well, wherein the emitter region is spaced apart from the JFET region by the well, implanting second conductivity type dopant ions to form a connector region of the second conductivity type adjacent the emitter region, forming a gate oxide layer on the channel region, and forming a gate on the gate oxide layer.

Claims

1. A method of forming an insulated gate bipolar transistor (IGBT) device, comprising:

forming a p-type drift layer;

forming an n-type well in the p-type drift layer;

epitaxially growing a p-type channel adjustment layer on the p-type drift layer and on the n-type well;

implanting p-type dopant ions to form a p-type emitter region that extends through the p-type channel adjustment layer and into the n-type well, the p-type emitter region at least partially defining a channel region in the n-type well adjacent the p-type emitter region;

implanting n-type dopant ions to form an n-type connector region that is adjacent the p-type emitter region and extends through the channel adjustment layer and into the n-type well;

forming a gate oxide layer on the channel region; and

forming a gate on the gate oxide layer.

2. The method of claim 1, further comprising annealing the p-type dopant implanted ions and the n-type dopant implanted ions.

3. The method of claim 2, further comprising:

forming a graphite coating on the channel adjustment layer, wherein the annealing the implanted ions comprises annealing the channel adjustment layer and the graphite coating; and

removing the graphite coating after the annealing the implanted ions.

4. The method of claim 3, further comprising crystallizing the graphite coating before the annealing the implanted ions.

5. The method of claim 3, wherein the annealing the implanted ions comprises annealing the implanted ions at a temperature greater than 1700°

C.

6. The method of claim 3, wherein the annealing the implanted ions comprises annealing the implanted ions at a temperature greater than 1800°

C.

7. The method of claim 1, wherein the forming the gate oxide layer comprises forming the gate oxide layer in dry O₂, the method further comprising annealing the gate oxide layer in wet O₂.

8. The method of claim 7, wherein the forming the gate oxide layer comprises forming the gate oxide layer in dry O₂ at a temperature less than or equal to about 1200°

C.

9. The method of claim 7, further comprising annealing the gate oxide layer in an inert atmosphere at a temperature less than or equal to about 1200°

C. after the forming the gate oxide layer and before the annealing the gate oxide layer in the wet O₂.

10. The method of claim 7, wherein the annealing the gate oxide layer in the wet O₂

comprises annealing the gate oxide layer in the wet O₂ at a temperature less than or equal to about 950°

C.

11. The method of claim 10, wherein the annealing the gate oxide layer in the wet O₂

comprises annealing the gate oxide layer in the wet O₂ for at least one hour.

12. The method of claim 7, wherein the annealing the gate oxide layer in the wet O₂ comprises generating pyrogenic steam in a pyrogenic chamber, supplying the pyrogenic steam to an anneal chamber, and annealing the gate oxide layer in the anneal chamber.

13. The method of claim 12, wherein the generating the pyrogenic steam comprises heating the pyrogenic chamber, supplying hydrogen and oxygen gas to the pyrogenic chamber, and combusting the hydrogen gas and the oxygen gas to form the pyrogenic steam, wherein the hydrogen gas and the oxygen gas are supplied to the pyrogenic chamber at a molecular ratio of hydrogen to oxygen of about 1.8 or more.

14. The method of claim 1, further comprising implanting p-type dopant ions into the drift layer to form a JFET region adjacent to the n-type well, and wherein the p-type emitter region is spaced apart from the JFET region and defines a channel region between the p-type emitter region and the JFET region.

15. The method of claim 1, wherein the channel adjustment layer is formed to have a thickness of about 0.1 μ

m to about 0.5 μ

m, and wherein the channel adjustment layer has a net acceptor concentration of about 1×

10¹⁶ cm<sup>−

3</sup> to about 5×

10¹⁸ cm<sup>−

3</sup>.

16. The method of claim 1, wherein the drift layer comprises an epitaxial silicon carbide layer.

17. The method of claim 1, where the forming the p-type drift layer comprises forming the p-type drift layer on an n-type substrate.

18. The method of claim 17, wherein the substrate comprises silicon carbide.

19. The method of claim 1, wherein a distance from a bottom of the p-type emitter region to a bottom of the n-type well region is equal to or greater than about 0.45 μ

m.

20. A method of forming an insulated gate bipolar transistor (IGBT) device, comprising:

forming a drift layer of a first conductivity type;

forming a well of a second conductivity type in the drift layer;

forming a JFET region with first conductivity type dopant ions in the drift layer;

forming a channel adjustment layer of the first conductivity type on the JFET region and the well;

implanting first conductivity type dopant ions to form an emitter region of the first conductivity type that extends through the channel adjustment layer and into the well, wherein the emitter region is spaced apart from the JFET region by the well;

implanting second conductivity type dopant ions to form a connector region of the second conductivity type that is adjacent the emitter region and into the well;

forming a gate oxide layer on the channel region; and

forming a gate on the gate oxide layer.

21. The method of claim 20, wherein the forming the JFET region comprises epitaxially growing the JFET region with additional first conductivity type dopant ions on the drift layer.

22. The method of claim 20, wherein the forming the JFET region comprises forming the JFET region with a dopant concentration of about 1×

10¹⁶ cm<sup>−

3</sup>.

23. The method of claim 20, wherein the forming the JFET region comprises implanting aluminum in the drift layer adjacent the well.

24. The method of claim 20, further comprising:

forming a graphite coating on the channel adjustment layer;

annealing the implanted ions in the channel adjustment layer;

annealing the graphite coating; and

removing the graphite coating after annealing the implanted ions.