Semiconductor device and method for manufacturing the same

• US 9,548,397 B2
• Filed: 06/22/2015
• Issued: 01/17/2017
• Est. Priority Date: 06/17/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Honda, Tatsuya
• Primary Examiner(s): Menz, Laura
• Application Number:
  US14/745,950
• Publication Number:
  US 20150287837A1
• Time in Patent Office: 575 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided.

Claims

1. A semiconductor device comprising:

an oxide semiconductor stack including a first oxide semiconductor layer, a second oxide semiconductor layer in contact with a top surface of the first oxide semiconductor layer, and a third oxide semiconductor layer in contact with a top surface of the second oxide semiconductor layer;

a source electrode layer and a drain electrode layer adjacent to the oxide semiconductor stack;

a gate insulating film adjacent to the oxide semiconductor stack; and

a gate electrode layer adjacent to the oxide semiconductor stack with the gate insulating film interposed therebetween,

wherein, in the oxide semiconductor stack, a region which does not overlap the source electrode layer or the drain electrode layer has a higher oxygen concentration than a region which overlaps the source electrode layer or the drain electrode layer, and

wherein the third oxide semiconductor layer covers side surfaces of the second oxide semiconductor layer and the first oxide semiconductor layer in a channel width direction.

2. The semiconductor device according to claim 1, wherein each of the first oxide semiconductor layer and the third oxide semiconductor layer contains indium, gallium and zinc, and the second oxide semiconductor layer contains indium, tin and zinc.

3. The semiconductor device according to claim 1, wherein an electron affinity of the second oxide semiconductor layer is higher than electron affinities of the first oxide semiconductor layer and the third oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein a region which is in the oxide semiconductor stack and does not overlap with the gate electrode layer contains dopant.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor stack is a c-axis aligned crystal oxide semiconductor film.

6. The semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of a table having a display portion, a television set, a computer, and a mobile phone.

7. A semiconductor device comprising:

an oxide semiconductor stack including a first oxide semiconductor layer, a second oxide semiconductor layer in contact with a top surface of the first oxide semiconductor layer, and a third oxide semiconductor layer in contact with a top surface of the second oxide semiconductor layer;

a source electrode layer and a drain electrode layer adjacent to the oxide semiconductor stack;

a gate insulating film over the oxide semiconductor stack; and

a gate electrode layer over the oxide semiconductor stack with the gate insulating film interposed therebetween,

wherein, in the oxide semiconductor stack, a region which does not overlap the source electrode layer or the drain electrode layer has a higher oxygen concentration than a region which overlaps the source electrode layer or the drain electrode layer, and

wherein the third oxide semiconductor layer covers side surfaces of the second oxide semiconductor layer and the first oxide semiconductor layer in a channel width direction.

8. The semiconductor device according to claim 7, wherein each of the first oxide semiconductor layer and the third oxide semiconductor layer contains indium, gallium and zinc, and the second oxide semiconductor layer contains indium, tin and zinc.

9. The semiconductor device according to claim 7, wherein an electron affinity of the second oxide semiconductor layer is higher than electron affinities of the first oxide semiconductor layer and the third oxide semiconductor layer.

10. The semiconductor device according to claim 7, wherein a region which is in the oxide semiconductor stack and does not overlap with the gate electrode layer contains dopant.

11. The semiconductor device according to claim 7, wherein the oxide semiconductor stack is a c-axis aligned crystal oxide semiconductor film.

12. The semiconductor device according to claim 7, wherein the semiconductor device is one selected from the group consisting of a table having a display portion, a television set, a computer, and a mobile phone.