Light emitting diode chip having multi microstructure substrate surface

• US 9,548,419 B2
• Filed: 10/23/2014
• Issued: 01/17/2017
• Est. Priority Date: 05/20/2014
• Status: Active Grant

• Current Assignee: Everlight Electronics Company Limited, Southern Taiwan University of Science and Technology
• Original Assignee: Everlight Electronics Company Limited, Southern Taiwan University of Science and Technology
• Inventors: Lee, Ming-Lun
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US14/521,471
• Publication Number:
  US 20150340558A1
• Time in Patent Office: 817 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/10 with a light reflecting structure, e.g. semiconductor Bragg reflector
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: H01L 33/56 Materials, e.g. epoxy or silicone resin
• CPC Class Codes: H01L 33/60 Reflective elements

Abstract

A light emitting diode chip including a substrate and a light emitting diode element layer is provided. The substrate has a growth surface and a plurality of microstructures on the growth surface, wherein an area of the growth surface occupied by the microstructures is A1 and an area of the growth surface not occupied by the micro-structures is A2, wherein A1 and A2 satisfies the relation of 0.1≦A2/(A1+A2)≦0.5. The light emitting diode element layer is disposed on the growth surface of the substrate.

Claims

1. A light emitting diode chip comprising:

a substrate, comprising a growth surface and a plurality of microstructures on the growth surface, wherein a first area of the growth surface occupied by the plurality of microstructures is A1 and a second area of the growth surface not occupied by the plurality of microstructures is A2, A1 and A2 satisfy the relation 0.1≦

A2/(A1+A2)≦

0.5, and a surface roughness of a surface of each microstructure of the plurality of microstructures and the growth surface does not exceed 10 nanometers; and

a light emitting diode element layer, disposed on the growth surface.

2. The light emitting diode chip of claim 1, wherein the plurality of microstructures comprises a plurality of protrusions.

3. The light emitting diode chip of claim 2, wherein a height of each protrusion of the plurality of protrusions is between 1 micron and 3 microns.

4. The light emitting diode chip of claim 2, wherein a height of each protrusion of the plurality of protrusions is between 1.2 micron and 2 microns.

5. The light emitting diode chip of claim 2, wherein each protrusion of the plurality of protrusions comprises a base connecting with the growth surface and the base has a width, and two neighboring bases maintain a distance therebetween, and a sum of the width and the distance is between 1 micron and 3 microns.

6. The light emitting diode chip of claim 5, wherein a distance between centroids of the two neighboring bases is between 1 micron and 3 microns.

7. The light emitting diode chip of claim 2, wherein each protrusion of the plurality of protrusions comprises a plurality of sectional surfaces parallel to the growth surface, and areas of the plurality of sectional surfaces progressively decrease along a height direction of each protrusion.

8. The light emitting diode chip of claim 7, wherein the areas of the plurality of sectional surfaces linearly decrease along the height direction of each protrusion.

9. The light emitting diode chip of claim 7, wherein the areas of the plurality of sectional surfaces decrease non-linearly along the direction of the height of each protrusion.

10. The light emitting diode chip of claim 1, wherein the plurality of microstructures comprises a plurality of depressions.

11. The light emitting diode chip of claim 10, wherein a depth of each depression of the plurality of depressions is between 1 micron and 3 microns.

12. The light emitting diode chip of claim 10, wherein a depth of each depression of the plurality of depressions is between 1.2 micron and 2 microns.

13. The light emitting diode chip of claim 10, each depression of the plurality of depressions comprises an opening connecting with the growth surface and the opening has a width, and two neighboring openings maintain a distance therebetween, and a sum of the width and the distance is between 1 micron and 3 microns.

14. The light emitting diode chip of claim 13, wherein a distance between centroids of the two neighboring openings is between 1 micron and 3 microns.

15. The light emitting diode chip of claim 10, wherein each depression of the plurality of depressions comprises a plurality of sectional surfaces parallel to the growth surface, and areas of the plurality of sectional surfaces progressively decrease along a depth direction of each depression.

16. The light emitting diode chip of claim 15, wherein the areas of the plurality of sectional surfaces linearly decrease along the depth direction of each depression.

17. The light emitting diode chip of claim 1, wherein the light emitting diode element layer further comprises:

a first conductivity type semiconductor layer, disposed on the growth surface;

a light emitting layer, disposed on the first conductivity type semiconductor layer; and

a second conductivity type semiconductor layer, disposed on the light emitting layer.

18. The light emitting diode chip of claim 17, wherein the light emitting device layer further comprises:

a buffer layer, disposed on the growth surface, the buffer layer is configured between the substrate and the first conductivity type semiconductor layer and encapsulating the plurality of protrusions.

19. The light emitting diode chip of claim 18, wherein a material of the buffer layer comprises aluminum nitride, gallium nitride, indium nitride, aluminum indium nitride, aluminum gallium nitride, aluminum gallium indium nitride, zirconium boride, or hafnium nitride.

20. The light emitting diode chip of claim 17, wherein one of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer comprises a P-type semiconductor layer and another one of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer comprises an N-type semiconductor layer.

21. The light emitting diode chip of claim 17, wherein the light emitting diode element layer further comprises:

a first electrode, electrically connected with the first conductivity type semiconductor layer; and

a second electrode, electrically connected with the second conductivity type semiconductor layer.

22. The light emitting diode chip of claim 21, wherein the light emitting diode element layer further comprises:

a transparent conductive layer, disposed on the second conductivity type semiconductor layer, and the second electrode is electrically connected with the second conductivity type conductor layer through the transparent conductive layer.

23. The light emitting diode chip of claim 22, wherein the light emitting diode element layer further comprises:

a reflective layer, disposed on the transparent conductive layer, and the transparent conductive layer is disposed between the reflective layer and the second conductivity type conductive layer.

24. The light emitting diode chip of claim 17, wherein the light emitting diode layer comprises a single quantum well structure or a multiple quantum well structure.