Power factor correction for constant current input with power line communication

• US 9,548,794 B2
• Filed: 05/03/2013
• Issued: 01/17/2017
• Est. Priority Date: 05/03/2013
• Status: Active Grant

• Current Assignee: Eaton Intelligent Power Limited (Eaton Corporation PLC.)
• Original Assignee: Cooper Technologies Company (Eaton Corporation PLC.)
• Inventors: Gumaer, Traver
• Primary Examiner(s): Han, Jessica
• Assistant Examiner(s): Gibson, Demetries A
• Application Number:
  US13/887,195
• Publication Number:
  US 20140328415A1
• Time in Patent Office: 1,355 Days
• Field of Search: 363/89, 363/73, 323/205, 323/315, 375/257
• US Class Current: 1/1
• CPC Class Codes: H02M 1/0054 Transistor switching losses periodically suspending operation of switching converter in low power mode H02M1/0035
• CPC Class Codes: H02M 1/0085 Partially controlled bridges
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04B 3/548 the power on the line being DC arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The present disclosure provides techniques for power factor correction on a constant current system and also provides power line communications on the same power factor correction circuit. In one example embodiment, through controlled charging and draining of an input capacitor, the power factor correction circuit generates an input voltage which is in phase with the input current. Communication data is also embedded in the input voltage and/or input current by further charging and draining of the input capacitor according to a controlled switching scheme which includes both input current phase data and corresponding communication signals.

Claims

1. A power factor correction circuit with power line communications, comprising:

an input capacitor configured to receive an input current from a constant current source and produce an input voltage, the input capacitor to be coupled in a parallel configuration with the constant current source;

a switching device coupled to the input capacitor, wherein the switching device switches between an OFF state and an ON state, and wherein the input voltage rises when the switching device is in the OFF state and drops when the switching device is in the ON state; and

a controller coupled to the switching device, wherein the controller controls switching of the switching device between the OFF state and the ON state, and the switching of the switching device shapes the input voltage to be in phase with the input current, and wherein the switching of the switching device generates disturbances on the input voltage and the input current, the disturbances having communication data.

2. The power factor correction circuit with power line communications of claim 1, further comprising:

a rectifier diode bridge configured to receive the input current from the constant current source and rectify the input current.

3. The power factor correction circuit with power line communications of claim 1, further comprising:

a first switching device coupled to the input capacitor, wherein the first switching device is operable during a first half cycle of the input current and shorted during a second half cycle of the input current, and switches between the OFF state and the ON state when operable;

a second switching device coupled to the input capacitor, wherein the second switching device is operable during the second half cycle of the input current and shorted during the first half cycle of the input current, and switches between the OFF state and the ON state when operable.

4. The power factor correction circuit with power line communications of claim 1, wherein the switching device comprises a MOSFET.

5. The power factor correction circuit with power line communications of claim 1, further comprising:

a DC output bus providing an output voltage, wherein the output voltage is a conditioned form of the input voltage, wherein the input voltage is in phase with the input current.

6. The power factor correction circuit with power line communications of claim 5, further comprising:

a first inductor coupled to the input capacitor, wherein the first inductor provides the output voltage during a first half cycle of the input current; and

a second inductor coupled to the input capacitor, wherein the second inductor provides the output voltage during a second half cycle of the input current.

7. The power factor correction circuit with power line communications of claim 1, wherein the controller produces a sine control waveform, the sine control waveform containing a desired voltage amplitude data, an input current phase data, and a communication data.

8. The power factor correction circuit with power line communications of claim 7, wherein the controller comprises a pulse width modulation (PWM) generator which receives the sine control waveform and generates a corresponding PWM signal, wherein the PWM signal is used to control switching of the switching device.

9. A power factor correction circuit with power line communications, comprising:

an input capacitor configured to receive an input current from a constant current source and produce an input voltage;

a switching device coupled to the input capacitor, wherein the switching device switches between an OFF state and an ON state, and wherein the input voltage rises when the switching device is in the OFF state and drops when the switching device is in the ON state; and

a controller coupled to the switching device and configured to receive a communication signal, wherein the controller controls switching of the switching device, and the switching of the switching device shapes the input voltage to be in phase with the input current, and wherein the switching of the switching device generates disturbances on the input voltage and the input current, the disturbances having communication data corresponding to the communication signal.

10. The power factor correction circuit with power line communications of claim 9, wherein the controller generates a sine wave reference synchronized with the input current and adds the communication signal to the sine wave reference.

11. The power factor correction circuit with power line communications of claim 9, wherein the controller comprises a pulse width modulation (PWM) generator that generates a PWM signal and wherein the PWM signal is used to control switching of the switching device.

12. The power factor correction circuit with power line communications of claim 9, further comprising a rectifier diode bridge configured to receive the input current from the constant current source and rectify the input current.

13. The power factor correction circuit with power line communications of claim 9, wherein the switching device comprises a MOSFET.

14. The power factor correction circuit with power line communications of claim 13, wherein when the MOSFET is in the OFF state, the input capacitor charges and the input voltage rises, and when the MOSFET is in the ON state, the input capacitor drains and the input voltage drops.

15. The power factor correction circuit with power line communications of claim 9, further comprising:

a first inductor coupled to the input capacitor, wherein the first inductor provides an output voltage during a first half cycle of the input current; and

a second inductor coupled to the input capacitor, wherein the second inductor provides the output voltage during a second half cycle of the input current, wherein the output voltage is a conditioned form of the input voltage and wherein the input voltage is in phase with the input current.