Information processing device, printing device, and control method

• US 9,552,050 B2
• Filed: 05/22/2015
• Issued: 01/24/2017
• Est. Priority Date: 06/02/2014
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Tsuchiya, Youji, Miyasaka, Masayo
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): Franklin, Richard B
• Application Number:
  US14/719,713
• Publication Number:
  US 20150346805A1
• Time in Patent Office: 613 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3284 Power saving in printer
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An information processing device having plural control units appropriately executes an arbitration process when a control unit is hibernating (in power-saving mode) and transmits data correctly to an external device. The information processing device has a first CPU and a second CPU; a first memory embedded in a semiconductor chip including the first CPU and second CPU; and a second memory disposed externally to the semiconductor chip. The first CPU executes an arbitration process according to the type of event that occurred when the first CPU is in a first state, the second CPU and the second memory are in a second state different from the first state, and an event requiring sending data from the first memory to the second memory occurs.

Claims

1. An information processing device with multiple operating modes, comprising:

a reception interface circuit including a first-in-first-out (FIFO) memory in which data sent from a host is first received and stored;

a data storage;

a controller; and

a dynamic memory access (DMA) circuit;

the controller reading data stored in the FIFO memory sequentially and transferring the data to, and storing the data in, the data storage when the operating mode is a first operating mode in which the controller is operating in a high speed state, and

the DMA circuit reading data stored in the FIFO memory sequentially without going through the controller, and transferring and storing the data in the data storage when the operating mode is a second operating mode in which the controller is operating in a low speed state.

2. The information processing device described in claim 1, further comprising:

a first CPU and a second CPU;

a first memory embedded in a semiconductor chip including the first CPU and second CPU; and

a second memory disposed externally to the semiconductor chip;

the controller including the first CPU;

the data storage including the first memory; and

the first CPU executing an arbitration process according to the type of event that occurred when the first CPU is operating in the high speed state, the second CPU and the second memory are operating in a low speed state, and an event requiring sending data from the first memory to the second memory occurs.

3. The information processing device described in claim 2, wherein:

the first CPU executes the arbitration process by

sending data from the first memory to the second memory when the event that occurred is a type one event,

storing data to be sent from the first memory to the second memory in the first memory when the event that occurred is a type two event, and

storing data to be sent from the first memory to the second memory in the first memory, and requesting the second CPU to enter a high speed state when the event that occurred is a type three event.

4. The information processing device described in claim 3, wherein:

the first CPU updates already stored data when the event that occurred is a type two event.

5. The information processing device described in claim 2, wherein:

the first CPU executes the arbitration process when the second CPU and second memory are changing to the high speed state or are changing to the low speed state.

6. The information processing device described in claim 2, wherein:

the storage capacity and power consumption of the second memory are greater than the storage capacity and power consumption of the first memory.

7. The information processing device described in claim 2, wherein:

the first CPU executes an operating system and program for the first CPU stored in the first memory; and

the second CPU executes an operating system and program for the second CPU stored in the second memory.

8. The information processing device described in claim 1, wherein:

the controller includes the first CPU; and

the clock frequency of the first CPU in the second operating mode is lower than the clock frequency in the first operating mode.

9. The information processing device described in claim 1, further comprising:

a third operating mode in which operation of the first CPU stops.

10. A printing device with multiple operating modes, comprising:

a print unit;

a reception interface circuit including a first-in-first-out (FIFO) memory in which data sent from a host is first received and stored;

a data storage;

a controller; and

a dynamic memory access (DMA) circuit;

the controller reading data stored in the FIFO memory sequentially and transferring the data to, and storing the data in, the data storage when the operating mode is a first operating mode in which the controller operating in a high speed state, and

the DMA circuit reading data stored in the FIFO memory sequentially without going through the controller, and transferring and storing the data in the data storage when the operating mode is a second operating mode in which the controller is operating in a low speed state.

11. The printing device described in claim 10, further comprising:

a first CPU and a second CPU;

a first memory embedded in a semiconductor chip including the first CPU and second CPU; and

a second memory disposed externally to the semiconductor chip;

the controller including the first CPU;

the data storage including the first memory; and

the first CPU executing an arbitration process according to the type of event that occurred when the first CPU is operating in the high speed state, the second CPU and the second memory are operating in a low speed state, and an event requiring sending data from the first memory to the second memory occurs.

12. The printing device described in claim 11, wherein:

the first CPU executes the arbitration process by

sending data from the first memory to the second memory when the event that occurred is a type one event unrelated to a printing process,

storing data to be sent from the first memory to the second memory in the first memory when the event that occurred is a type two event that at least transmits information related to communication, and

storing data to be sent from the first memory to the second memory in the first memory, and requesting the second CPU to enter a high speed state when the event that occurred is a type three event that receives a print request.

13. The printing device described in claim 10, wherein:

the controller includes the first CPU; and

the clock frequency of the first CPU in the second operating mode is lower than the clock frequency in the first operating mode.

14. A control method of an information processing device with multiple operating modes, wherein:

the information processing device has a reception interface circuit including a first-in-first-out (FIFO) memory to which data sent from a host is first received and stored, a data storage, a contoller, and a dynamic memory access (DMA) circuit, and the control method includes

the controller reading data stored in the FIFO memory sequentially and transferring the data to, and storing the data in, the data storage when the operating mode is a first operating mode in which the controller is in a high speed state, and

the DMA circuit reading data stored in the FIFO memory sequentially without going through the controller and transferring the data to, and storing the data in, the data storage when the operating mode is a second operating mode in which the controller is operating in a low speed state.

15. The control method described in claim 14, wherein:

the information processing device has a first CPU and a second CPU, a first memory embedded in a semiconductor chip including the first CPU and second CPU, and a second memory disposed externally to the semiconductor chip;

the controller includes the first CPU;

the data storage includes the first memory; and

the control method includes the first CPU executing an arbitration process according to the type of event that occurred when the first CPU is in the high speed state, the second CPU and the second memory are in a low speed state, and an event requiring sending data from the first memory to the second memory occurs.