Systems and methods for rapid processing and storage of data

• US 9,552,299 B2
• Filed: 06/10/2011
• Issued: 01/24/2017
• Est. Priority Date: 06/11/2010
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Stalzer, Mark A.
• Primary Examiner(s): TSAI, SHENG JEN
• Application Number:
  US13/158,161
• Publication Number:
  US 20110307647A1
• Time in Patent Office: 2,055 Days
• Field of Search: 711/103, 711/118
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/224 Disk storage
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric

Abstract

Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.

Claims

1. A server, comprising:

a plurality of computing complexes;

a processor configured to communicate with the plurality of computing complexes interconnected by an on-server router;

wherein each computing complex comprises;

a system on chip including;

at least one general processing core and an associated cache memory,

an accelerator, and

a RAID memory controller,

wherein the system on chip is packaged with Package on Package memory; and

a non-volatile memory component configured in a RAID configuration that is separate from and connected to the system on chip;

wherein a general processing core in a given computing complex is configured to use the RAID memory controller to directly read and write data to the non-volatile memory component within the given computing complex, which cannot be directly written to and read from by general processing cores within other computing complexes in the plurality of computing complexes;

wherein general processing cores in the plurality of computing complexes are configured to directly read from and write data to the non-volatile memory component to which they are connected in parallel;

wherein the on-server router is configured to connect the computing complexes using individual interconnects;

wherein the on-server router includes an interconnect to the processor and an interconnect to at least one port to a high performance network fabric for off-blade communications;

wherein the processor is configured to broadcast lookup requests with respect to data stored within the plurality of computing complexes to the general purpose processing cores within the plurality of computing complexes via the on-server router;

wherein the general processing cores are configured to search in parallel for data requested by the lookup requests using an index that has been distributed to each computing complex and stored in the Package on Package memory of each computing complex; and

wherein the server is configured to communicate with external devices via the high performance network fabric.

2. The server of claim 1, wherein the non-volatile memory component is NAND Flash memory.

3. The server of claim 2, wherein the computing complex is configured to communicate with the non-volatile memory component at a rate of at least 200 MB/s.

4. The server of claim 1, wherein the at least one general processing core is a RISC processor.

5. The server of claim 1, wherein the RAID memory controller is configured to communicate at a rate of at least 500 MB/s.

6. The server of claim 1, comprising at least 32 computing complexes.

7. The server of claim 1, wherein each interconnect is configured to provide data rates of at least 500 MB/s.

8. The server of claim 1, wherein the interconnect between the on-server router and the processor is configured to provide data rates of at least 25 GB/s.

13. The server of claim 1, wherein each of the at least one non-volatile memory components dedicated to a computing complex is packaged by Package on Package to the computing complex.

14. The server of claim 1, wherein a first computing complex is configured to access data within a non-volatile memory component that is dedicated to a second computing complex by requesting the data from the second computing complex via the on-server router.

17. The server of claim 1, wherein the RAID configuration is implemented using a software RAID configuration is implemented across all of the non-volatile memory components of each of the plurality of computing complexes.

9. A massively parallel computing system, comprising:

at least one Solid State Server configured to communicate with at least one other Solid State Server via a high performance network fabric;

wherein each Solid State Server comprises a plurality of computing complexes interconnected by an on-server router and a processor configured to communicate with the plurality of computing complexes via the on-server router;

wherein each computing complex comprises;

a system on chip including;

at least one general processing core and an associated cache memory,

an accelerator, and

a RAID memory controller,

wherein the system on chip is packaged with Package on Package memory; and

a non-volatile memory component configured in a RAID configuration that is separate from and connected to the system on chip;

wherein a general processing core in a given computing complex is configured to use the RAID memory controller to directly read and write data to the non-volatile memory component within the given computing complex, which cannot be directly written to and read from by general processing cores within other computing complexes in the plurality of computing complexes;

wherein general processing cores in the plurality of computing complexes are configured to directly read from and write data to the non-volatile memory component to which they are connected in parallel;

wherein the on-server router is configured to connect the computing complexes using individual interconnects; and

wherein the on-server router includes an interconnect to the processor and an interconnect to at least one port to the high performance network fabric for off-blade communications; and

wherein the processor is configured to broadcast lookup requests with respect to data stored within the plurality of computing complexes to the general purpose processing cores within the plurality of computing complexes via the on-server router; and

wherein the general processing cores are configured to search in parallel for data requested by the lookup requests using an index that has been distributed to each computing complex and stored in the Package on Package memory of each computing complex.

10. The massively parallel computing system of claim 9, wherein pluralities of the computing complexes are directly connected.

11. The massively parallel computing system of claim 9, comprising a plurality of Solid State Servers interconnected via the high performance network fabric.

15. The massively parallel computing system of claim 9, wherein each of the at least one non-volatile memory components dedicated to a computing complex is packaged by Package on Package to the computing complex.

16. The massively parallel computing system of claim 9, wherein a first computing complex is configured to access data within a non-volatile memory component that is dedicated to a second computing complex by requesting the data from the second computing complex via the on-server router.

12. A massively parallel computing system, comprising:

a plurality of servers interconnected via a high performance network fabric, where at least one of the servers is a Solid State Server;

wherein each Solid State Server comprises a plurality of computing complexes interconnected by an on-server router and a processor configured to communicate with the plurality of computing complexes via the on-server router;

wherein each computing complex comprises;

a system on chip including;

at least one general processing core and an associated cache memory,

an accelerator, and

a RAID memory controller,

wherein the system on chip is packaged with Package on Package memory; and

a non-volatile memory component configured in a RAID configuration that is separate from and connected to the system on chip;

wherein a general processing core in a given computing complex is configured to use the RAID memory controller to directly read and write to the non-volatile memory component within the given computing complex, which cannot be directly written to and read from by general processing cores within other computing complexes in the plurality of computing complexes;

wherein general processing cores in the plurality of computing complexes are configured to directly read from and write data to the non-volatile memory component to which they are connected in parallel;

wherein the on-server router is configured to connect the computing complexes using individual interconnects;

wherein the on-server router includes an interconnect to the processor and an interconnect to at least one port to the high performance network fabric for off-blade communications; and

wherein the processor is configured to broadcast lookup requests with respect to data stored within the plurality of computing complexes to the general purpose processing cores within the plurality of computing complexes via the on-server router; and

wherein the general processing cores are configured to search in parallel for data requested by the lookup requests using an index that has been distributed to each computing complex and stored in the Package on Package memory of each computing complex.