Method and apparatus for flip chip packaging co-design and co-designed flip chip package
First Claim
1. A method for flip chip packaging co-design, the method comprising steps of:
- providing an Input/Output (I/O) pad information of a chip and a connection information of a PCB;
performing an I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB;
utilizing a redistribution layer (RDL) routing analysis device to perform a bump pad pitch analysis for the I/O pad placement of the chip to generate a bump pad pitch analysis result;
performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and
adjusting the I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.
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Abstract
The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.
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Citations
20 Claims
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1. A method for flip chip packaging co-design, the method comprising steps of:
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providing an Input/Output (I/O) pad information of a chip and a connection information of a PCB; performing an I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a redistribution layer (RDL) routing analysis device to perform a bump pad pitch analysis for the I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and adjusting the I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus for flip chip packaging co-design, the apparatus comprising:
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an I/O pad placement device, for performing an I/O pad placement according to an I/O pad information of a chip and a connection information of a PCB; a redistribution layer (RDL) routing analysis device, for performing a bump pad pitch analysis for the I/O pad placement of the chip to generate a bump pad pitch analysis result; and an bump pad planning device, for performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and wherein the I/O pad placement device adjusts the I/O pad placement for the chip according to the bump pad planning result. - View Dependent Claims (12, 13, 14, 15)
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16. A co-designed flip chip package, comprising:
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a chip, having an Input/Output (I/O) pad information; a PCB, having a connection information; and an I/O pad placement, disposed according to the I/O pad information of the chip and the connection information of the PCB; wherein a redistribution layer (RDL) routing analysis device is utilized for performing a bump pad pitch analysis for the I/O pad placement of the chip to generate a bump pad pitch analysis result; and
an bump pad planning device is utilized for performing a bump pad planning for a package according to the bump pad pitch analysis result. - View Dependent Claims (17, 18, 19, 20)
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Specification