Electronic apparatus and display driver

• US 9,552,786 B2
• Filed: 03/23/2015
• Issued: 01/24/2017
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Synaptics Japan GK (Synaptics Incorporated)
• Original Assignee: Synaptics Japan GK (Synaptics Incorporated)
• Inventors: Shikata, Atsushi
• Primary Examiner(s): DINH, DUC Q
• Application Number:
  US14/665,386
• Publication Number:
  US 20150279295A1
• Time in Patent Office: 673 Days
• Field of Search: 345/204, 345/209, 345/690, 345/211, 345/212, 345/213
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0823 used to establish symmetry in driving, e.g. with polarity inversion
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

In case that a terminal gradation signal output terminal in a pre-stage display driver and an initial gradation signal output terminal in a next-stage display driver of a plurality of display drivers which are arranged in parallel are used in driving the same gradation signal electrode of a display panel, an output of dummy data from the other gradation signal output terminal which mutually competes with an output timing of a gradation signal from one gradation signal output terminal between both the gradation signal output terminals is suppressed by high impedance control of a corresponding gradation signal output terminal.

Claims

1. An electronic apparatus comprising:

a display panel; and

a plurality of display drivers which are disposed in series at an edge of the display panel in order to drive the display panel,

wherein the display panel includes a plurality of sub-pixels in which selection terminals are connected to scanning signal electrodes and signal input terminals are connected to gradation signal electrodes, and wherein the plurality of sub-pixels form a plurality of scanning lines that extend in a direction of the scanning signal electrodes and a plurality of signal lines that extend in a direction of the gradation signal electrodes, and wherein the sub-pixels in a same signal line are alternately connected to adjacent gradation signal electrodes that are disposed on one of a first side of the same signal line and a second, opposite side of the same signal line,

the display drivers are configured to supply gradation signals to a plurality of gradation signal electrodes in a parallel manner while driving the scanning signal electrodes in a predetermined order,

wherein a first gradation signal output terminal disposed on a first display driver of the plurality of display drivers is adjacent to a second gradation signal output terminal disposed on a second display driver of the plurality of display drivers, wherein the first and second gradation signal output terminals are connected to a common gradation signal electrode of the gradation signal electrodes, and

wherein the first and second display drivers are adjacently located to each other at the edge of the display panel and suppress an output of dummy data from the first and second gradation signal output terminals by using high impedance control associated with the first and second gradation signal output terminals to control an output of a gradation signal onto the common gradation signal electrode.

2. The electronic apparatus according to claim 1, wherein each of the display drivers includes a plurality of first output buffers that output a gradation signal of a first polarity to the gradation signal electrodes and a plurality of second output buffers that output a gradation signal of a second polarity, and includes an output switch circuit that switchably connects outputs of the first output buffers and the second output buffers to corresponding gradation signal output terminals.

3. The electronic apparatus according to claim 2, wherein every other sub-pixel in the same signal line is alternatively connected to adjacent gradation signal electrodes, and

wherein the display drivers are configured to drive the gradation signal electrodes with the same polarity at an interval of one electrode using a plurality of the first output buffers and the second output buffers, and alternately switches drive polarities of the gradation signal electrodes in units of display frames.

4. The electronic apparatus according to claim 3, wherein the display panel includes an active element comprising a thin film transistor for each of the sub-pixels, the active element comprising amorphous silicon, and

wherein the gradation signal output terminals correspond to the gradation signal electrodes one to one.

5. The electronic apparatus according to claim 3, wherein the display panel includes an active element comprising a thin film transistor for each of the sub-pixels, the active element comprising low-temperature polysilicon,

wherein a respective gradation signal output terminal is allocated for each of three gradation signal electrodes of Red, Green, and Blue driven with the same polarity at an interval of one electrode with an input switch circuit interposed therebetween, and

wherein the display drivers are configured to switch one of the gradation signal electrodes connected to a respective gradation signal output terminal in the input switch circuit in synchronization with switching of a driven scanning signal electrode.

6. The electronic apparatus according to claim 2, wherein one of the first output buffers and one of the second output buffers are configured to connect to the first and second gradation signal output terminals and are configured such that a slew rate of at least one of the gradation signal of the first and second polarities is capable of being selected in accordance with a selection signal.

7. The electronic apparatus according to claim 2, further comprising a host device that supplies display data to the plurality of display drivers,

wherein the plurality of display drivers each include a common circuit configuration, and

the host device divides a series of gradation data for each scanning line and supplies the divided data to each of the display drivers.

8. The electronic apparatus according to claim 1, wherein the first display driver is configured to place a first buffer coupled to the first gradation signal output terminal in a high impedance state based on a first high impedance control signal and the second display driver is configured to place a second buffer coupled to the second gradation signal output terminal in a low impedance state based on a second high impedance control signal such that only one of the first and second buffer outputs the gradation signal onto the common gradation signal electrode.

9. The electronic apparatus according to claim 8, wherein the first high impedance control signal is inverted relative to the second high impedance control signal.

10. The electronic apparatus according to claim 8, wherein the first and second high impedance control signals are derived based on transitions of a selection signal used to select a particular color of the plurality of sub-pixels to update in the display panel.

11. The electronic apparatus according to claim 1, the first and second gradation signal output terminals do not output dummy data.

12. A display driver comprising:

a plurality of gradation signal output terminals, arranged in parallel, configured to output gradation signals in a parallel manner;

a plurality of first output buffers configured to output a first gradation signal of a first polarity to the gradation signal output terminals;

a plurality of second output buffers configured to output a second gradation signal of a second polarity to the gradation signal output terminals;

an output switch circuit configured to switchably connect the first output buffers and second output buffers to corresponding gradation signal output terminals; and

a timing control circuit configured to control an output of a third gradation signal to a corresponding gradation signal output terminal from each of the first output buffers and the second output buffers in synchronization with display timing while alternately switching a switch state of the output switch circuit at a predetermined timing,

wherein outputs of the first output buffers and the second output buffers that are selectively connected to gradation signal output terminals located on opposite ends of the display driver are configured to be selectively controlled in a high impedance state, and

wherein the timing control circuit is configured to control the outputs in the high impedance state based on a dummy data output timing of one of the first output buffers and the second output buffers that are selectively connected to the gradation signal output terminals located on opposite ends of the display driver.

13. The display driver according to claim 12, wherein the predetermined timing is a timing which is synchronized with switching of a display frame.

14. The display driver according to claim 12, wherein one of the first output buffer and the second output buffer that are selectively connected to the gradation signal output terminals located on opposite ends of the display driver is configured such that a slew rate of one of the first and second gradation signal is capable of being selected in accordance with a selection signal.

15. The display driver according to claim 12, wherein the output switch circuit is configured to drive gradation signal electrodes with a same polarity at an interval of one electrode using the first and second output buffers, and alternately switches drive polarities of the gradation signal electrodes in units of display frames.

16. The display driver according to claim 12, wherein the first output buffers and the second output buffers that are selectively connected to gradation signal output terminals located on opposite ends of the display driver do not output dummy data.

17. A display driver which is formed in one semiconductor substrate, the display driver comprising:

a plurality of gradation signal output terminals, arranged in parallel, configured to output gradation signals in a parallel manner;

a plurality of first output buffers configured to output a first gradation signal of a first polarity to the gradation signal output terminals;

a plurality of second output buffers configured to output a second gradation signal of a second polarity to the gradation signal output terminals;

an output switch circuit configured to switchably connect the first output buffers and second output buffers to corresponding gradation signal output terminals; and

a timing control circuit configured to control an output of a third gradation signal to a corresponding gradation signal output terminal from each of the first output buffers and the second output buffers in synchronization with display timing while alternately switching a switch state of the output switch circuit at a predetermined timing,

wherein outputs of the first output buffers and the second output buffers that are selectively connected to gradation signal output terminals located on opposite ends of the display driver are configured to be selectively controlled in a high impedance state, and

wherein the timing control circuit is configured to suppress an output of dummy data from at least one of the first output buffers and at least one of the second output buffers that are selectively connected to the gradation signal output terminals located on opposite ends of the display driver by using a high impedance control signal of the at least one of the first output buffers and the at least one of the second output buffers.

18. The display driver according to claim 17, wherein the predetermined timing is a timing which is synchronized with switching of a display frame.

19. The display driver according to claim 17, wherein the output switch circuit is configured to drive gradation signal electrodes with a same polarity at an interval of one electrode using the first and second output buffers, and alternately switches drive polarities of the gradation signal electrodes in units of display frames.

20. The display driver according to claim 17, wherein the first output buffers and the second output buffers that are selectively connected to gradation signal output terminals located on opposite ends of the display driver do not output dummy data.