Nonvolatile memory device having variable resistance memory cells and a method of resetting by initially performing pre-read or strong set operation

• US 9,552,879 B2
• Filed: 10/03/2014
• Issued: 01/24/2017
• Est. Priority Date: 02/21/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Yongkyu, Lee, Yeongtaek, Kim, Youngbae
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US14/505,523
• Publication Number:
  US 20150243353A1
• Time in Patent Office: 844 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5614 using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result

Abstract

A method of resetting a variable resistance memory cell in a nonvolatile memory device includes; programming the memory cell to a set state using a corresponding compliance current, and then programming the memory cell to a reset state by pre-reading the variable resistance memory cell to determine its resistance and resetting the memory cell using a variable reset voltage determined in response to the determined resistance.

Claims

1. A method of programming a variable resistance memory cell in a nonvolatile memory device, the method comprising:

programming the variable resistance memory cell to one of a plurality of set states using a corresponding one of a plurality of compliance currents;

pre-reading the variable resistance memory cell to determine the resistance of the variable resistance memory cell; and

programming the variable resistance memory cell to a reset state using a variable reset voltage based on the determined resistance of the variable resistance memory cell, wherein

the variable reset voltage is one of a plurality of reset voltages respectively corresponding to the plurality of set states.

2. The method of claim 1, wherein the determined resistance of the variable resistance memory cell is one of a plurality of resistance ranges respectively corresponding to the plurality of set states.

3. The method of claim 2, wherein the plurality of set states comprises a first set state indicated by a first resistance range, a second set state indicated by a second resistance range greater than the first resistance range, and a third set state indicated by a third resistance range greater than the second resistance range.

4. The method of claim 3, wherein the plurality of reset voltages comprises a first reset voltage used to reset the variable resistance memory cell to the reset state when programmed to the first set state, a second reset voltage less than the first reset voltage and used to reset the variable resistance memory cell to the reset state when programmed to the second set state, and a third reset voltage less than the second reset voltage and used to reset the variable resistance memory cell to the reset state when programmed to the third set state.

5. The method of claim 4, wherein the variable resistance memory cell is programmed to the first set state using a first compliance current, the variable resistance memory cell is programmed to the second set state using a second compliance current greater than the first compliance current, and the variable resistance memory cell is programmed to the third set state using a third compliance current greater than the second compliance current.

6. The method of claim 1, wherein the pre-read operation is performed in response to an external command received by the nonvolatile memory device.

7. The method of claim 1, wherein the pre-read operation is performed periodically.

8. The method of claim 1, wherein the variable resistance memory cell includes a data storage film comprising a bipolar resistance memory material.

9. A method of programming a variable resistance memory cell in a nonvolatile memory device, the method comprising:

programming the variable resistance memory cell to one of a plurality of set states using a corresponding one of a plurality of compliance currents;

programming the variable resistance memory cell to a strong set state using a variable voltage based on a resistance of the variable resistance memory cell; and

programming the variable resistance memory cell to a reset state from the strong set state using a constant reset voltage.

10. The method of claim 9, wherein:

the plurality of set states comprises a first set state indicated by a first resistance range, a second set state indicated by a second resistance range greater than the first resistance range, and a third set state indicated by a third resistance range greater than the second resistance range, and

the variable resistance memory cell is programmed to the first set state using a first compliance current, the variable resistance memory cell is programmed to the second set state using a second compliance current greater than the first compliance current, and the variable resistance memory cell is programmed to the third set state using a third compliance current greater than the second compliance current.

11. The method of claim 9, wherein the nonvolatile memory device comprises a memory cell array including the variable resistance memory cell, the memory cell array being arranged in a three-dimensional structure.

12. A method of programming a variable resistance memory cell in a nonvolatile memory device, the method comprising:

programming the variable resistance memory cell to one of a plurality of set states using a corresponding one of a plurality of compliance currents;

pre-reading the variable resistance memory cell to determine the resistance of the variable resistance memory cell;

programming the variable resistance memory cell to a strong set state using a variable voltage based on the determined resistance of the variable resistance memory cell; and

programming the variable resistance memory cell to a reset state from the strong set state using a constant reset voltage.

13. The method of claim 12, wherein the determined resistance of the variable resistance memory cell is one of a plurality of resistance ranges respectively corresponding to the plurality of set states.

14. The method of claim 12, wherein the plurality of set states comprises a first set state indicated by a first resistance range, a second set state indicated by a second resistance range greater than the first resistance range, and a third set state indicated by a third resistance range greater than the second resistance range.

15. The method of claim 14, wherein the variable resistance memory cell is programmed to the first set state using a first compliance current, the variable resistance memory cell is programmed to the second set state using a second compliance current greater than the first compliance current, and the variable resistance memory cell is programmed to the third set state using a third compliance current greater than the second compliance current.

16. The method of claim 12, wherein the pre-read operation is performed in response to an external command received by the nonvolatile memory device.

17. The method of claim 12, wherein the pre-read operation is performed periodically.

18. The method of claim 12, wherein the variable resistance memory cell includes a data storage film comprising a bipolar resistance memory material.

19. The method of claim 12, wherein the nonvolatile memory device comprises a memory cell array including the variable resistance memory cell, the memory cell array being arranged in a three-dimensional structure.