Antifuse with bypass diode and method thereof

• US 9,552,890 B2
• Filed: 02/25/2014
• Issued: 01/24/2017
• Est. Priority Date: 02/25/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Pigott, John M., Gray, Randall C.
• Primary Examiner(s): Crawford, Latanya N
• Application Number:
  US14/189,529
• Publication Number:
  US 20150243365A1
• Time in Patent Office: 1,064 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. In such an embodiment the first diode effectively provides a bypass current path that can reduce the voltage across the antifuse when other antifuses are being programmed. As such, these embodiments can provide improved ability to tolerate programming voltages without damage or impairment of reliability.

Claims

1. A semiconductor device comprising:

an antifuse having a first node and a second node;

a first diode having a first diode anode and a first diode cathode, the first diode cathode coupled to the first node of the antifuse, and the first diode anode coupled to the second node of the antifuse such that the first diode and the antifuse are in a parallel combination; and

a second diode coupled in series with the parallel combination, where the second diode is coupled oppositely biased compared to the first diode, and where the first diode has a first area, and the second diode has a second area, and wherein the second area is at least twice as large as the first area.

2. The semiconductor device of claim 1 wherein the second diode includes a second diode anode and a second diode cathode, and wherein the second diode is coupled in series with the parallel combination by the second diode cathode being coupled to the first node of the antifuse.

3. The semiconductor device of claim 2 wherein the second diode anode is selectively coupled to a programming voltage source for programming the antifuse.

4. The semiconductor device of claim 1 wherein the second diode includes a second diode anode and a second diode cathode, and wherein the second diode is coupled in series with the parallel combination by the second diode anode being coupled to the second node of the antifuse.

5. The semiconductor device of claim 4 wherein the first node of the antifuse is selectively coupled to a programming voltage source for programming the antifuse.

6. The semiconductor device of claim 1 where the first diode has a first area, and the second diode as a second area, and wherein the second area is sufficient to carry a programming current, and wherein the first area is sufficient to carry a leakage current.

7. The semiconductor device of claim 1 wherein the antifuse comprises:

a substrate material;

a gate electrode positioned above the substrate material; and

an insulating layer disposed between the gate electrode and the substrate material such that voltage applied between the gate electrode and the substrate material causes a rupture in the insulating layer and creates a current path through the insulating layer.

8. A semiconductor device, comprising:

an array of antifuse bitcells, each antifuse bitcell comprising;

an antifuse having a first node and a second node,

a first diode having a first diode anode and a first diode cathode, the first diode cathode coupled to the first node of the antifuse, and the first diode anode coupled to the second node of the antifuse such that the first diode and the antifuse are in a parallel combination, and

a second diode coupled in series with the parallel combination; and

driver circuitry configure to selectively program the array of antifuse bitcells by selectively applying a programming voltage to a selected antifuse bitcell.

9. The semiconductor device of claim 8 wherein the second diode includes a second diode anode and a second diode cathode, and wherein the second diode is coupled in series with the parallel combination by the second diode cathode being coupled to the first node of the antifuse.

10. The semiconductor device of claim 9 wherein the driver circuitry is coupled to the second diode anode for selectively applying the programming voltage to the selected antifuse bitcell.

11. The semiconductor device of claim 8 wherein the second diode includes a second diode anode and a second diode cathode, and wherein the second diode is coupled in series with the parallel combination by the second diode anode being coupled to the second node of the antifuse.

12. The semiconductor device of claim 11 wherein the driver circuitry is coupled to the first node of the antifuse for selectively applying the programming voltage to the selected antifuse bitcell.

13. The semiconductor device of claim 8 where the first diode has a first area, and the second diode as a second area, and wherein the first area is at least twice as large as the second area.

14. The semiconductor device of claim 8 wherein the semiconductor device is formed in a substrate material, and wherein each antifuse in the array of antifuse bitcells comprises:

a gate electrode positioned above the substrate material; and

an insulating layer disposed between the gate electrode and the substrate material such that voltage applied between the gate electrode and the substrate material causes a rupture in the insulating layer and creates a current path through the insulating layer.

15. A semiconductor device comprising:

an antifuse having a first node and a second node;

a first diode having a first diode anode and a first diode cathode, the first diode cathode coupled to the first node of the antifuse, and the first diode anode coupled to the second node of the antifuse such that the first diode and the antifuse are in a parallel combination; and

a second diode coupled in series with the parallel combination, where the first diode has a first area, and the second diode has a second area, and wherein the second area is at least twice as large as the first area.

16. The semiconductor device of claim 15 wherein the second diode includes a second diode anode and a second diode cathode, and wherein the second diode is coupled in series with the parallel combination by the second diode cathode being coupled to the first node of the antifuse, wherein the second diode anode is selectively coupled to a programming voltage source for programming the antifuse.

17. The semiconductor device of claim 15 wherein the second diode includes a second diode anode and a second diode cathode, and wherein the second diode is coupled in series with the parallel combination by the second diode anode being coupled to the second node of the antifuse, wherein the first node of the antifuse is selectively coupled to a programming voltage source for programming the antifuse.

18. The semiconductor device of claim 15 where the second area is sufficient to carry a programming current, and wherein the first area is sufficient to carry a leakage current.

19. The semiconductor device of claim 15 wherein the antifuse comprises:

a substrate material;

a gate electrode positioned above the substrate material; and

an insulating layer disposed between the gate electrode and the substrate material such that voltage applied between the gate electrode and the substrate material causes a rupture in the insulating layer and creates a current path through the insulating layer.