Bumps for chip scale packaging including under bump metal structures with different diameters

• US 9,553,065 B2
• Filed: 03/11/2014
• Issued: 01/24/2017
• Est. Priority Date: 11/11/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chun-Hung, Chen, Yu-Feng, Lin, Tsung-Shu, Pu, Han-Ping, Chen, Hsien-Wei
• Primary Examiner(s): Islam, Mohammad
• Assistant Examiner(s): Chang, Jay C
• Application Number:
  US14/204,659
• Publication Number:
  US 20140191394A1
• Time in Patent Office: 1,050 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0233 Structure of the redistribution layers
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05085 with additional elements, e.g. vias arrays, interposed between the stacked layers
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/14132 : being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/14135 : Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/14136 : Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/14179 : Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.

Claims

1. A device comprising:

a semiconductor die comprising a substrate, electrical circuits formed along a first side of the substrate and a redistribution layer over the first side of the substrate;

a plurality of under bump metal structures arranged in rows and columns on a center region of a top surface of the substrate;

a first under bump metal structure formed in a first region of the semiconductor die, wherein the first under bump metal structure is of a first diameter and a bottom of the first under bump metal structure is in direct contact with the redistribution layer, and wherein the first under bump metal structure is electrically connected to the electrical circuits through a first metal line in a bottom metallization layer, a second metal line in a top metallization layer, a via in a passivation layer, an aluminum pad in a first polymer layer and the redistribution layer;

a second under bump metal structure formed in a second region of the semiconductor die, wherein the second under bump metal structure is of a second diameter and a bottom of the second under bump metal structure is in direct contact with the redistribution layer, and wherein the second under bump metal structure and the first under bump metal structure are immediately adjacent to each other;

a third under bump metal structure having a third diameter formed in the second region of the semiconductor die, wherein the second under bump metal structure and the third under bump metal structure are in a same row and immediately adjacent to each other, and wherein the third diameter is equal to the second diameter and the first diameter is greater than the second diameter;

a fourth under bump metal structure having the first diameter, wherein the fourth under bump metal structure and the first under bump metal structure are in an outermost column of the plurality of under bump metal structures and are immediately adjacent to each other;

a fifth under bump metal structure having the first diameter, wherein the fourth under bump metal structure and the fifth under bump metal structure are in an outermost row of the plurality of under bump metal structures and are immediately adjacent to each other, and wherein a distance between the fourth under bump metal structure and the fifth under bump metal structure is greater than a distance between the second under bump metal structure and the third under bump metal structure;

a first bump formed over the first under bump metal structure; and

a second bump formed over the second under bump metal structure, wherein a top surface of the first bump is level with a top surface of the second bump, and wherein a first sidewall of an edge portion of the second under bump metal structure is covered by the second bump and a second sidewall of the edge portion of the second under bump metal structure is not covered by the second bump.

2. The device of claim 1, wherein:

the first region is an outer region of the semiconductor die; and

the second region is an inner region of the semiconductor die.

3. The device of claim 2, wherein:

the outer region has a width approximately equal to or less than one third of a width of the inner region.

4. The device of claim 2, wherein:

the second diameter is less than or equal to 90% of the first diameter.

5. The device of claim 1, wherein:

the first bump is formed of solder; and

the second bump is formed of solder.

6. The device of claim 1, wherein:

the first bump is of an hourglass shape.

7. The device of claim 1, wherein:

the second bump has a diameter greater than a diameter of the first bump.

8. A device comprising:

a semiconductor die comprising a substrate, electrical circuits formed along a first side of the substrate and a redistribution layer over the first side of the substrate, wherein the redistribution layer comprising a redistribution line;

a first under bump metal structure formed adjacent to an edge of the semiconductor die and over the first side of the substrate, wherein the redistribution layer is connected between an aluminum pad and a bottom of the first under bump metal structure, and wherein the first under bump metal structure is electrically connected to the electrical circuits through a first metal line in a bottom metallization layer, a second metal line in a top metallization layer, a via in a passivation layer, the aluminum pad in a first polymer layer and the redistribution line;

a second under bump metal structure formed not adjacent to the edge of the semiconductor die, wherein the first under bump metal structure has a diameter greater than a diameter of the second under bump metal structure;

a first bump formed over the first under bump metal structure, wherein a sidewall of the first bump comprises a first slope portion, a vertical sidewall portion and a second slope portion, and wherein an edge portion of the first under bump metal structure is not completely covered by the first bump, and wherein the edge portion of the first under bump metal structure extends from an outermost edge of the redistribution line to an outermost edge of the first under bump metal structure; and

a second bump formed over the second under bump metal structure, wherein the second bump is of a spherical shape, and wherein a top surface of the first bump is level with a top surface of the second bump, and wherein a first sidewall of an edge portion of the second under bump metal structure is covered by the second bump and a second sidewall of the edge portion of the second under bump metal structure is not covered by the second bump.

9. The device of claim 8, wherein:

the second bump has a diameter greater than a diameter of the first bump.

10. The device of claim 8, wherein:

the first under bump metal structure is formed on an outer region of the semiconductor die; and

the second under bump metal structure is formed on an inner region of the semiconductor die.

11. The device of claim 10, wherein:

the outer region has a width approximately equal to or less than one third of a width of the inner region.

12. A device comprising:

a plurality of small under bump metal structures arranged in rows and columns on a center region of a top surface of a substrate, wherein the plurality of small under bump metal structures are of a same diameter;

a first row of large under bump metal structures between a first edge of the center region and a first edge of the substrate, wherein the first row comprises a first under bump metal structure and a second under bump metal structure adjacent to each other;

a second row of large under bump metal structures between a second edge of the center region and a second edge of the substrate, wherein the first edge and the second edge of the center region are on opposite sides of the center region;

a first column of large under bump metal structures between a third edge of the center region and a third edge of the substrate, wherein the first column comprises the first under bump metal structure and a third under bump metal structure adjacent to each other;

a second column of large under bump metal structures between a fourth edge of the center region and a fourth edge of the substrate, wherein the third edge and the fourth edge of the center region are on opposite sides of the center region, and wherein a distance between two immediately adjacent large under bump metal structures is greater than a distance between two immediately adjacent small under bump metal structures, and

wherein each of the large under bump metal structures has a diameter greater than a diameter of each of the small under bump metal structures;

a redistribution line under and in contact with a large under bump metal structure;

a first bump formed over the large under bump metal structure, wherein an edge portion of the large under bump metal structure is not completely covered by the first bump, and wherein the edge portion of the large under bump metal structure extends from an outermost edge of the redistribution line to an outermost edge of the large under bump metal structure; and

a second bump formed over a small under bump metal structure, wherein a first sidewall of an edge portion of the small under bump metal structure is covered by the second bump and a second sidewall of the edge portion of the small under bump metal structure is not covered by the second bump.

13. The device of claim 12, wherein:

a top surface of the first bump is level with a top surface of the second bump.

14. The device of claim 12, wherein:

the small under bump metal structure is immediately next to the large under bump metal structure.

15. The device of claim 12, wherein:

the first under bump metal structure is at a corner of the top surface of the substrate.

16. The device of claim 12, wherein:

large under bump metal structures of the first row, the second row, the first column and the second column are of a same diameter.

17. The device of claim 12, wherein:

the first bump is of an hourglass shape.

18. The device of claim 12, wherein:

the second bump is of a spherical shape.