Semiconductor device and insulated gate bipolar transistor with barrier structure

• US 9,553,179 B2
• Filed: 01/31/2014
• Issued: 01/24/2017
• Est. Priority Date: 01/31/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Vellei, Antonio, Laven, Johannes Georg, Baburske, Roman, Philippou, Alexander
• Primary Examiner(s): Le, Thao X
• Assistant Examiner(s): OJEH, NDUKA E
• Application Number:
  US14/169,712
• Publication Number:
  US 20150221756A1
• Time in Patent Office: 1,089 Days
• Field of Search: 257471-486, 257607-612, 257/E29.001, 257/E29.066, 257/E29.197, 257/E29.262, 257/E21.41, 438/133, 438/208, 438/220, 438/356, 438/570, 438/270, 438/589, 438/FOR.122, 438/FOR.123, 438/FOR.149
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a semiconductor mesa which is formed between cell trench structures extending from a first surface into a semiconductor body. The semiconductor mesa includes a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface. Source zones are arranged along a longitudinal axis of the semiconductor mesa at a first distance from each other and form second pn junctions with the body zone. A barrier structure, which has the conductivity type of the source zones, forms at least one of a unipolar homojunction with the drift zone and a pn junction with the body zone at least outside a vertical projection of the source zones perpendicular to the first surface. The barrier structure may be absent in the vertical projection of the source zones.

Claims

1. A semiconductor device, comprising:

a continuous semiconductor mesa formed between cell trench structures extending from a first surface into a semiconductor body, the semiconductor mesa comprising a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface;

separated source zones formed in the semiconductor mesa at a first distance from each other along a longitudinal axis of the semiconductor mesa and forming second pn junctions with the body zone, wherein the longitudinal axis extends in a direction of the length of the semiconductor mesa and between the separated source zones the body zone directly adjoins the first surface; and

a barrier structure in a portion of the semiconductor mesa between neighboring ones of the separated source zones, the barrier structure being absent at least in a vertical projection of the separated source zones perpendicular to the first surface and forming a unipolar homojunction with the drift zone outside of the vertical projection of the separated source zones.

2. The semiconductor device of claim 1, wherein

the barrier structure directly adjoins both the body zone and the drift zone and forms a unipolar homojunction with the drifts zone and a pn-junction with the body zone.

3. The semiconductor device of claim 1, wherein

the barrier structure is spatially separated from the body zone and forms a unipolar homojunction with the drift zone.

4. The semiconductor device of claim 1, wherein

the barrier structure is spatially separated from the drift zone and forms a pn junction with the body zone.

5. The semiconductor device of claim 1, wherein

the barrier structure is formed along at most 95% of the first distance.

6. The semiconductor device of claim 1, wherein

the barrier structure is formed at an offset from the separated source zones along the longitudinal axis, the offset being in a range from 0.5% to 40% of the first distance.

7. The semiconductor device of claim 1, wherein

the barrier structure includes at least two barrier zones which are spatially separated from each other along the longitudinal axis.

8. The semiconductor device of claim 7, wherein

a gap between the barrier zones along the longitudinal axis has a width in a range from 5% to 40% of the first distance.

9. The semiconductor device of claim 1, wherein

a net impurity concentration of the barrier structure is symmetric with reference to a vertical symmetry plane between two of the separated source zones perpendicular to the first surface.

10. The semiconductor device of claim 1, wherein

at least one of the cell trench structures comprises a gate structure arranged to form an inversion layer through the body zone between the source and drift zones, respectively in a first state and to form no inversion layer through the body zone in a second state.

11. The semiconductor device of claim 1, wherein

the semiconductor device is or comprises an insulated gate bipolar transistor comprising a field effect transistor cell.

12. The semiconductor device of claim 1, wherein

the semiconductor device is or comprises a reverse conducting insulated gate bipolar transistor that comprises a collector layer comprising first zones of a first conductivity type as well as second zones of a second conductivity type complementary to the first conductivity type between the drift zone and a second surface of the semiconductor body opposite to the first surface.

13. The semiconductor device of claim 1, wherein

the barrier structure contains impurities of a deep level donor or deep double donor.

14. The semiconductor device of claim 1, wherein

a mean net impurity concentration in the barrier structure is at least ten times as high as a mean net impurity concentration in the drift zone.

15. The semiconductor device of claim 1, wherein

the body zone includes segments separated along a longitudinal axis of the respective semiconductor mesa by regions of the conductivity type of the separated source zones.

16. The semiconductor device of claim 15, wherein

the regions of the conductivity type of the separated source zones form the barrier structure.

17. A semiconductor device, comprising:

a continuous semiconductor mesa formed between cell trench structures extending from a first surface into a semiconductor body, the semiconductor mesa comprising a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface;

separated source zones formed in the semiconductor mesa at a first distance from each other along a longitudinal axis of the semiconductor mesa and forming second pn junctions with the body zone, wherein between the separated source zones the body zone directly adjoins the first surface and wherein the longitudinal axis is parallel to the first surface, parallel to an interface between the semiconductor mesa and the cell trench structures, and extends in a direction of the length of the semiconductor mesa; and

a barrier structure in a portion of the semiconductor mesa between neighboring ones of the separated source zones, the barrier structure being separated from the drift zone and forming a pn junction with the body zone.

18. The semiconductor device of claim 17, wherein

the barrier structure is formed outside a vertical projection of the separated source zones and is absent at least in the vertical projection of the separated source zones.

19. The semiconductor device of claim 17, wherein

the barrier structure is a contiguous structure including first portions outside a vertical projection of the separated source zones and second portions in the vertical projection of the separated source zones.

20. A semiconductor device, comprising:

a continuous semiconductor mesa formed between cell trench structures extending from a first surface into a semiconductor body, the semiconductor mesa comprising a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface;

separated source zones formed in the semiconductor mesa at a first distance from each other along a longitudinal axis of the semiconductor mesa and forming second pn junctions with the body zone, wherein the longitudinal axis extends in a direction of the length of the semiconductor mesa and between the separated source zones the body zone directly adjoins the first surface; and

a contiguous barrier structure of the conductivity type of the separated source zones, the contiguous barrier structure being disposed in the semiconductor mesa, being not interrupted along the longitudinal axis and forming, in the semiconductor mesa, a unipolar homojunction with the drift zone, wherein

a net impurity concentration of the barrier structure continuously or in steps varies by at least 20% along the longitudinal axis between centers of two neighboring ones of the separated source zones.

21. The semiconductor device of claim 20, wherein

the semiconductor device is an RC-IGBT or a semiconductor diode and the net impurity concentration in the barrier structure increases along the longitudinal axis with decreasing distance to the separated source zones.

22. The semiconductor device of claim 20, wherein

the semiconductor device is a non-RC-IGBT and the net impurity concentration in the barrier structure decreases along the longitudinal axis with decreasing distance to the separated source zones.

23. The semiconductor device of claim 20, wherein

the net impurity concentration of the barrier structure is symmetric with reference to a vertical symmetry plane between the two neighboring ones of the separated source zones perpendicular to the first surface.

24. The semiconductor device of claim 20, wherein

the contiguous barrier structure is present in the vertical projection of the separated source zones.