Low power buffer with dynamic gain control

• US 9,553,569 B1
• Filed: 02/04/2015
• Issued: 01/24/2017
• Est. Priority Date: 02/04/2015
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Inphi Corporation
• Inventors: Gorecki, James Lawrence, Tan, Han-Yuan
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US14/614,253
• Time in Patent Office: 720 Days
• US Class Current: 1/1
• CPC Class Codes: H03F 3/3001 with field-effect transistors
• CPC Class Codes: H03F 3/3033 NMOS SEPP output stages H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03G 3/20 Automatic control H03G3/005 takes precedence; combined with volume compression or expansion H03G7/00
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 5/01 Shaping pulses discrimination against noise or interference H03K5/125
• CPC Class Codes: H03K 5/02 by amplifying H03K5/04 takes precedence
• CPC Class Codes: H03K 5/023 using field effect transistors
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H04B 1/16 Circuits

Abstract

The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.

Claims

1. A buffer circuit comprising:

a first input node to receive a first input signal;

a second input node to receive a second input signal;

a first connection node;

a first supply node;

a first transistor coupled to the first input node, the first supply node, and the first connection node;

a second transistor coupled to the second input node and the first connection node; and

a first current shunt circuit coupled to the second transistor;

a gain control node coupled to the first current shunt circuit to receive a gain control signal;

a replica buffer coupled to the gain control node to serve as a proxy for the buffer circuit;

wherein the second input signal is a complement of the first input signal, and

wherein the first current shunt circuit shunts a first bypass current around the second transistor to adjust a gain of the buffer circuit, and

wherein the gain is defined by an output amplitude of a first output signal at the first connection node divided by an input amplitude of the first input signal.

2. The buffer circuit of claim 1, wherein at least one of the first transistor, the second transistor, and the first current shunt circuit comprise an N-type MOSFET device.

3. The buffer circuit of claim 1, further comprising:

a gain control node coupled to the first current shunt circuit to receive a gain control signal; and

a gain control module coupled to the gain control node to provide the gain control signal;

wherein the gain control signal biases the first current shunt circuit to set the gain to a target gain.

4. The buffer circuit of claim 3, the gain control module further comprising:

a gain DAC coupled to the gain control node to convert a first digital representation of the gain control signal to the gain control signal; and

a calibration circuit coupled to the gain DAC to receive a second digital representation of the gain and generate the first digital representation of the gain control signal;

wherein the first digital representation of the gain control signal generated by the calibration circuit is determined, in part, by the second digital representation of the gain.

5. The buffer circuit of claim 1, further comprising:

a second connection node;

a second supply node;

a third transistor coupled to the second input node, the second supply node, and the second connection node;

a fourth transistor coupled to the first input node and the second connection node; and

a second current shunt circuit coupled to the fourth transistor;

wherein the first current shunt circuit shunts a first bypass current around the second transistor and the second current shunt circuit shunts a second bypass current around the fourth transistor to adjust a differential gain of the buffer circuit, wherein the differential gain is defined by a differential output amplitude of a differential output signal divided by a differential input amplitude of a differential input signal, wherein the differential output signal is the difference between the first output signal at the first connection node and a second output signal at the second connection node, and the differential input signal is the difference between the first input signal and the second input signal.

6. The buffer circuit of claim 5, wherein at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the first current shunt circuit, and the second current shunt circuit comprise an N-type MOSFET device.

7. The buffer circuit of claim 5, further comprising:

a gain control node coupled to the first current shunt circuit and the second current shunt circuit to receive a gain control signal; and

a gain control module coupled to the gain control node to provide the gain control signal;

wherein the gain control signal biases the first current shunt circuit and the second current shunt circuit to set the gain to a target gain.

8. The buffer circuit of claim 7, the gain control module further comprising:

a replica buffer coupled to the gain control node to serve as a proxy for the buffer circuit; and

a difference amplifier coupled to the replica buffer and the gain control node to measure a replica buffer gain of the replica buffer and to generate the gain control signal;

wherein the gain control signal generated by the difference amplifier sets the replica buffer gain of the replica buffer to the target gain.

9. The buffer circuit of claim 7, the gain control module further comprising:

a gain DAC coupled to the gain control node to convert a first digital representation of the gain control signal to the gain control signal; and

a calibration circuit coupled to the gain DAC to receive a second digital representation of the gain and generate the first digital representation of the gain control signal;

wherein the first digital representation of the gain control signal generated by the calibration circuit is determined, in part, by the second digital representation of the gain.

10. A buffer circuit comprising:

a first input node to receive a first input signal;

a second input node to receive a second input signal;

a first connection node;

a first supply node;

a first transistor coupled to the first input node, the first supply node, and the first connection node;

a second transistor coupled to the second input node and the first connection node; and

a first current shunt circuit coupled to the second transistor;

a gain control node coupled to the first current shunt circuit to receive a gain control signal; and

a gain control module coupled to the gain control node to provide the gain control signal;

wherein the gain control signal biases the first current shunt circuit to set the gain to a target gain, and

wherein the second input signal is a complement of the first input signal, and

wherein the first current shunt circuit shunts a first bypass current around the second transistor to adjust a gain of the buffer circuit, and

wherein the gain is defined by an output amplitude of a first output signal at the first connection node divided by an input amplitude of the first input signal, and wherein the gain control module further comprising;

a replica buffer coupled to the gain control node to serve as a proxy for the buffer circuit; and

a difference amplifier coupled to the replica buffer and the gain control node to measure a replica buffer gain of the replica buffer and to generate the gain control signal;

wherein the gain control signal generated by the difference amplifier sets the replica buffer gain of the replica buffer to the target gain.

11. A buffer circuit comprising:

a first input node to receive a first input signal;

a second input node to receive a second input signal;

a first connection node;

a third connection node;

a first supply node;

a first current feedback node;

a first transistor coupled to the first input node, the first supply node, and the first connection node;

a second transistor coupled to the second input node and the first connection node;

a fifth transistor coupled to the first connection node, the first supply node, and the third connection node;

a sixth transistor coupled to the first input node, the first current feedback node, and the third connection node;

a first current mirror coupled to the first current feedback node and the first supply node;

a first current shunt circuit coupled to the second transistor; and

a third current shunt circuit coupled to the sixth transistor;

wherein the second input signal is a complement of the first input signal, and

wherein the first current shunt circuit shunts a first bypass current around the second transistor and the third current shunt circuit shunts a third bypass current around the sixth transistor to adjust a gain of the buffer circuit, and

wherein the gain is defined by an output amplitude of a first output signal at the first supply node divided by an input amplitude of the first input signal.

12. The buffer circuit of claim 11, wherein at least one of the first transistor, the second transistor, the sixth transistor, the first current shunt circuit, and the third current shunt circuit comprise an N-type MOSFET device, and the fifth transistor comprises a P-type MOSFET device.

13. The buffer circuit of claim 11, further comprising:

a gain control node coupled to the first current shunt circuit and the third current shunt circuit to receive a gain control signal; and

a gain control module coupled to the gain control node to provide the gain control signal;

wherein the gain control signal biases the first current shunt circuit and the third current shunt circuit to set the gain to a target gain.

14. The buffer circuit of claim 13, the gain control module further comprising:

a replica buffer coupled to the gain control node to serve as a proxy for the buffer circuit; and

a difference amplifier coupled to the replica buffer and the gain control node to measure a replica buffer gain of the replica buffer and to generate the gain control signal;

wherein the gain control signal generated by the difference amplifier sets the replica buffer gain of the replica buffer to the target gain.

15. The buffer circuit of claim 13, the gain control module further comprising:

a gain DAC coupled to the gain control node to convert a first digital representation of the gain control signal to the gain control signal; and

a calibration circuit coupled to the gain DAC to receive a second digital representation of the gain and generate the first digital representation of the gain control signal;

wherein the first digital representation of the gain control signal generated by the calibration circuit is determined, in part, by the second digital representation of the gain.

16. The buffer circuit of claim 11, further comprising:

a second connection node;

a fourth connection node;

a second supply node;

a second current feedback node;

a third transistor coupled to the second input node, the second supply node, and the second connection node;

a fourth transistor coupled to the first input node and the second connection node;

a seventh transistor coupled to the second connection node, the second supply node, and the fourth connection node;

an eighth transistor coupled to the second input node, the second current feedback node, and the fourth connection node;

a second current mirror coupled to the second current feedback node and the second supply node;

a second current shunt circuit coupled to the fourth transistor; and

a fourth current shunt circuit coupled to the eighth transistor;

wherein the first current shunt circuit shunts the first bypass current around the second transistor, the second current shunt circuit shunts a second bypass current around the fourth transistor, the third current shunt circuit shunts the third bypass current around the sixth transistor, and the fourth current shunt circuit shunts a fourth bypass current around the eighth transistor to adjust a differential gain of the buffer circuit, wherein the differential gain is defined by a differential output amplitude of a differential output signal divided by a differential input amplitude of a differential input signal, wherein the differential output signal is the difference between the first output signal at the first supply node and a second output signal at the second supply node, and the differential input signal is the difference between the first input signal and the second input signal.

17. The buffer circuit of claim 16, wherein at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor, the eighth transistor, the first current shunt circuit, the second current shunt circuit, the third current shunt circuit, and the fourth current shunt circuit comprise an N-type MOSFET device, and at least one of the fifth transistor and the seventh transistor comprise a P-type MOSFET device.

18. The buffer circuit of claim 16, further comprising:

a gain control node coupled to the first current shunt circuit, the second current shunt circuit, the third shunt circuit, and the fourth shunt circuit to receive a gain control signal; and

a gain control module coupled to the gain control node to provide the gain control signal;

wherein the gain control signal biases the first current shunt circuit, the second current shunt circuit, the third shunt circuit, and the fourth shunt circuit to set the gain to a target gain.

19. The buffer circuit of claim 18, the gain control module further comprising:

a replica buffer coupled to the gain control node to serve as a proxy for the buffer circuit; and

a difference amplifier coupled to the replica buffer and the gain control node to measure a replica buffer gain of the replica buffer and to generate the gain control signal;

wherein the gain control signal generated by the difference amplifier sets the replica buffer gain of the replica buffer to the target gain.

20. The buffer circuit of claim 18, the gain control module further comprising:

a gain DAC coupled to the gain control node to convert a first digital representation of the gain control signal to the gain control signal; and

a calibration circuit coupled to the gain DAC to receive a second digital representation of the gain and generate the first digital representation of the gain control signal;

wherein the first digital representation of the gain control signal generated by the calibration circuit is determined, in part, by the second digital representation of the gain.