Methods and systems for analog-to-digital conversion (ADC) using an ultra small capacitor array with full range and sub-range modes

• US 9,553,602 B1
• Filed: 03/21/2016
• Issued: 01/24/2017
• Est. Priority Date: 03/21/2016
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Wu, I-chang, Bal, Jagdeep
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US15/076,327
• Time in Patent Office: 309 Days
• Field of Search: 341/156, 341/155, 341/144, 341/110, 341/120, 341/108, 341/172
• US Class Current: 1/1
• CPC Class Codes: H03M 1/0617 characterised by the use of methods or means not specific to a particular type of detrimental influence
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/146 all stages being simultaneous converters
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array

Abstract

Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal and a digital N-bit output signal. A local charge-averaging capacitor array (LCACA) is configured to receive the control signal and a reference voltage. An output of the LCACA is coupled to the first low input. The first LCACA is divided into a high sub-array and a low sub-array. The high sub-array is pre-charged to a high reference voltage and the low sub-array is pre-charged to a low reference voltage. The high reference voltage is greater than the low reference voltage. In operation, an analog signal is input to the first high input and the digital N-bit output signal is the digital conversion of the analog signal.

Claims

1. An apparatus comprising:

a comparator, the comparator is configured with a first high input, a first low input, and is configure to receive a clock signal;

a logic/latch block, the logic/latch block is configured to receive the clock signal and an output from the comparator, the logic/latch block is configured to output a control signal and a digital N-bit output signal; and

a first local charge-averaging capacitor array (LCACA), the first LCACA is configured to receive the control signal and a reference voltage, an output of the first LCACA is coupled to the first low input, the first LCACA is divided into a high sub-array and a low sub-array, the high sub-array to be pre-charged to a high reference voltage and the low sub-array to be pre-charged to a low reference voltage, the high reference voltage is greater than the low reference voltage, wherein in operation an analog signal is input to the first high input and the digital N-bit output signal is the digital conversion of the analog signal.

2. The apparatus of claim 1, wherein the logic/latch block is operable to provide control signals to the first LCACA array and to compute a comparison voltage (Vq) for N cycles before outputting the digital N-bit output signal.

3. The apparatus of claim 1, wherein the clock signal is an internal clock signal formed using a replica circuit of an LCACA charging state and an internal signal from the comparator.

4. The apparatus of claim 1, wherein the LCACA is structured according to a number of bits “

b”

required in the analog-to-digital conversion as follows;

b=2,N₂=2;

b>

2,N_b=N_b-1+Round(N_b-1/2);

n=1,K₁(b)=Round(N_b-1/2); and

n>

1,K_n(b)=K_n-1(b−

1).

5. The apparatus of claim 1, wherein the comparator is configured with a differential input, the comparator further comprising:

a second high input and a second low input, wherein an analog differential signal is input to the first high input and the second low input; and

a second local charge-averaging capacitor array (LCACA), the second LCACA is configured to receive a second control signal from the logic/latch block and a second reference voltage, an output of the second LCACA is coupled to the second high input, wherein in operation the analog differential signal is input to the comparator and the digital N-bit output signal is a digital conversion of the analog differential signal.

6. The apparatus of claim 1, wherein the clock signal is configured to sample the analog input signal at a frequency sufficient to satisfy the Nyquist condition.

7. The apparatus of claim 1, wherein the clock signal is designed to sample the analog input signal at a frequency below the Nyquist condition.

8. The apparatus of claim 1, wherein the clock signal is sufficiently high to accommodate a bandwidth of multiple Giga-hertz for the analog input signal.

9. An apparatus comprising:

an M-bit analog-to-digital converter (ADC), the M-Bit ADC is configured to receive an input analog signal and to assign the input analog signal to a first section of an M-bit digital output signal having 2^M sections, a residue voltage and at least one reference voltage;

an N-bit analog-to-digital converter (ADC), the N-bit ADC is configured to receive as an input the residue voltage and the at least one reference voltage, the N-bit ADC converter further comprising;

a comparator, the comparator is configured to receive the output signal on a first high input, the comparator has a first low input, and the comparator is configure to receive a clock signal;

a logic/latch block, the logic/latch block is configured to receive the clock signal and an output signal from the comparator, the logic/latch block is configured to output a control signal and a digital N-bit output signal; and

a local charge-averaging capacitor array (LCACA), the LCACA is configured to receive the residue voltage and the at least one reference voltage, an output signal of the LCACA is coupled to the first low input, the LCACA is divided into a left sub-array and a right sub-array, the left sub-array and the right sub-array are pre-charged to different voltages in a predefined order according to section number, wherein in operation the output signal of the LCACA is input on the first high input and the digital conversion of the analog signal contains M+N bits.

10. The apparatus of claim 9, wherein in sub-ranging mode the M-bit ADC is disabled, the input to the N-bit ADC and the reference voltages are provided by a previous stage.

11. The apparatus of claim 9, wherein the clock signal is an internal clock signal formed using a replica circuit of the LCACA charging state and an internal signal from the comparator.

12. The apparatus of claim 9, wherein a sense amplifier is used in the comparator.

13. A method for converting an input analog signal to digital comprising:

pre-charging a least significant bit (LSB) sub-array of a local charge-averaging capacitor array (LCACA) to a first voltage;

pre-charging a most significant bit (MSB) sub-array of the local charge-averaging capacitor array (LCACA) to a second voltage, wherein the second voltage is greater than the first voltage;

selecting a first number of capacitors from the LCACA to produce an average voltage;

analyzing an output of a comparator in response to the average voltage; and

repeating the steps of selecting a number of capacitors from the LCACA and analyzing an output of a comparator to identify a digital output representative of a voltage of the input analog signal.

14. The method of claim 13 wherein the steps of selecting a number of capacitors from the LCACA to produce an average voltage, analyzing an output of a comparator in response to the average voltage, and repeating the steps of selecting a number of capacitors from the LCACA and analyzing an output of a comparator to identify a digital output representative of the voltage of the input analog signal further comprise:

combining in parallel K1 capacitors [CH(0)˜

CH(K1)] from the MSB sub-array and K1 capacitors [CL(0)˜

CL(1)] from the LSB sub-array to obtain Vq(n) for n=1;

testing A (if Vi>

Vq(n)) then

(yes or

     1) n=n+1,

C_min(n)=CH(K1−

K2)

C_max(n)=CH(K1+K2−

1)

combine in parallel C_min(n)˜

C_max(n) to obtain Vq(n)

GO TO Testing B

(no or

     0) n=n+1

C_min(n)=CL(K1−

K2)

C_max(n)=CL(K1+K2−

1)

combine in parallel C_min(n)˜

C_max(n) to obtain Vq(n)

testing B (if Vi>

Vq(n)) then

(yes or

     1) if n>

N then

(yes or

     1) END

(no or

     0) n=n+1

C_min(n)=C_max(n−

1)+1−

K(n)

C_max(n)=C_max(n−

1)+K(n)

combine in parallel C_min(n)˜

C_max(n) to obtain

Vq(n)

GO TO testing B

(no or

     0) if n>

N then

(yes or

     1) END

(no or

     0) n=n+1

C_min(n)=C_min(n−

1)−

K(n)

C_max(n)=C_min(n−

1)−

1+K(n)

combine in parallel C_min(n)˜

C_max(n) to obtain

Vq(n)

GO TO testing B.

15. The method of claim 14, wherein Vi is output from a separate M-bit analog-to-digital converter (ADC).

16. The method of claim 14, wherein Vi is output from a previous stage.

17. A logic implemented in an integrated circuit, the logic to convert an input analog signal to digital, the logic comprising:

pre-charging means for pre-charging a least significant bit (LSB) sub-array of a local charge-averaging capacitor array (LCACA) to a first voltage and for pre-charging a most significant bit (MSB) sub-array of the local charge-averaging capacitor array (LCACA) to a second voltage, wherein the second voltage is greater than the first voltage;

means for selecting a first number of capacitors from the LCACA to produce an average voltage;

means for analyzing an output of a comparator in response to the average voltage; and

means for determining whether to repeat the selecting with a second number of capacitors and the analyzing an output of the comparator.

18. The logic of claim 17, further comprising:

means for ordering a most significant bit (MSB) direction in the LCACA as a function of section number associated with the input analog signal; and

means for producing a digital output from the LCACA.

19. The logic of claim 17, further comprising:

means for creating an internal clock with a replica circuit of an LCACA charging state and an internal signal from the comparator.

20. The logic of claim 19, wherein the internal clock signal is sufficiently high to accommodate a bandwidth of multiple Giga-hertz for the input analog signal.