Capacitive MEMS sensor and method

• US 9,556,016 B2
• Filed: 08/17/2013
• Issued: 01/31/2017
• Est. Priority Date: 08/20/2012
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Feyh, Ando
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): KLEIN, JORDAN M
• Application Number:
  US13/969,525
• Publication Number:
  US 20150360933A1
• Time in Patent Office: 1,263 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2203/04 Electrodes
• CPC Class Codes: B81B 3/0027 Structures for transforming mechanical energy, e.g. potential energy of a spring into translation, sound into translation
• CPC Class Codes: B81C 1/00166 Electrodes
• CPC Class Codes: B81C 1/0038 Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• CPC Class Codes: G01L 9/0045 Diaphragm associated with a buried cavity
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm

Abstract

A system and method for forming a sensor device includes defining an in-plane electrode in a device layer of a silicon on insulator (SOI) wafer, forming an out-of-plane electrode in a silicon cap layer located above an upper surface of the device layer, depositing a silicide-forming metal on a top surface of the silicon cap layer, and annealing the deposited silicide-forming metal to form a silicide portion in the silicon cap layer.

Claims

1. A method of forming a sensor device, comprising:

defining an in-plane electrode in a device layer of a silicon on insulator (SOI) wafer;

forming an out-of-plane electrode in a silicon cap layer located above an upper surface of the device layer by forming at least one non-silicon spacer in the cap layer;

depositing a silicide-forming metal on a top surface of the silicon cap layer and on a top surface of the at least one non-silicon spacer; and

annealing the deposited silicide-forming metal to form a silicide portion in the silicon cap layer.

2. The method of claim 1, wherein annealing the deposited silicide-forming metal comprises rapid thermal annealing the deposited silicide-forming metal.

3. The method of claim 1, further comprising:

etching a residual silicide-forming metal from the top surface of the silicon cap layer.

4. The method of claim 1, wherein depositing the silicide-forming metal comprises:

depositing a silicide-forming metal selected from a group consisting of nickel, tantalum, titanium, tungsten, and platinum.

5. The method of claim 1, wherein annealing the deposited silicide-forming metal comprises:

annealing the deposited silicide-forming metal for a duration between 1 second and 10 minutes.

6. The method of claim 1, wherein annealing the deposited silicide-forming metal comprises:

annealing the deposited silicide-forming metal at a temperature in a range of 250°

C. to 800°

C.

7. The method of claim 6, wherein the annealing temperature is less than 450°

C.

8. The method of claim 1, wherein annealing the deposited silicide-forming metal comprises:

annealing the deposited silicide-forming metal such that the entire cap layer is converted to silicide.

9. The method of claim 1, further comprising:

removing a portion of the silicide-forming metal deposited on the top surface of the at least one non-silicon spacer in the cap layer after annealing the silicide-forming metal.

10. The method of claim 1, further comprising:

supporting the cap layer with the device layer at a location above the defined in-plane electrode prior to forming the out-of-plane electrode.

11. The method of claim 10, further comprising:

forming a device layer connector portion within the device layer in electrical communication with the defined in-plane electrode; and

forming a cap layer connector portion within the supported cap layer, the cap layer connector portion in electrical communication with the device layer connector portion.

12. The method of claim 1, further comprising:

placing the formed silicide portion in the silicon cap layer in electrical communication with a piezo-resistor.

13. A sensor device, comprising:

an in-plane electrode;

a cap layer spaced apart from an upper surface of the in-plane electrode;

an out-of-plane electrode defined in the cap layer by at least one first non-silicon spacer;

a connector portion defined in the cap layer and in electrical communication with the in-plane electrode, the connector portion having a silicide upper surface; and

a silicide portion formed in the cap layer.

14. The sensor device of claim 13, wherein the silicide portion and the silicide upper surface are formed in the cap layer by annealing a silicide-forming metal deposited on a top surface of the cap layer.

15. The sensor device of claim 14, wherein the silicide-forming metal is one or more of nickel, tantalum, titanium, tungsten, and platinum.

16. The sensor device of claim 13, wherein the sensor device is a pressure sensor device and the silicide portion is formed throughout an entire depth of the cap layer.

17. The sensor device of claim 13, further comprising:

at least one piezo-resistor, wherein the silicide portion is formed in a top portion of the cap layer in electrical communication with the at least one piezo-resistor so as to provide an electrical connection to the at least one piezo-resistor.

18. The sensor device of claim 13, further comprising:

a second non-silicon spacer extending downwardly from an upper surface of the cap layer, the second non-silicon spacer electrically isolating the silicide portion from the silicide upper surface.