Nanochannel electrode devices

• US 9,557,290 B2
• Filed: 01/04/2016
• Issued: 01/31/2017
• Est. Priority Date: 08/06/2014
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Cheng, Kangguo, Ervin, Joseph, Li, Juntao, Pei, Chengwen, Wang, Geng
• Primary Examiner(s): Pham, Long
• Application Number:
  US14/987,329
• Publication Number:
  US 20160116435A1
• Time in Patent Office: 393 Days
• US Class Current: 1/1
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 33/48721 Investigating individual macromolecules, e.g. by translocation through nanopores Coulter counters in general G01N15/12; fabrication methods for nanoscale apertures B81B1/00; sequencing of nucleic acids C12Q1/68
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B

Abstract

A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

Claims

1. A method of forming:

a structure comprising;

forming a pair of parallel electrodes on a substrate, wherein each of said pair of parallel electrodes comprises at least a semiconductor fin, wherein a nanochannel is formed between said pair of parallel electrodes;

forming a metal interconnect structure-containing layer comprising conductive structures embedded in at least one dielectric material layer, each of said conductive structures is electrically shorted to one of said pair of parallel electrodes; and

forming a contiguous cavity passing through said substrate and said metal interconnect structure-containing layer, and said contiguous cavity comprising said nanochannel.

2. The method of claim 1, further comprising disposing a medium located within said contiguous cavity.

3. The method of claim 2, further comprising:

disposing a first external electrode and a second external electrode on said medium said first external electrode being disposed above a top surface of said substrate and said second external electrode being disposed below said top surface of said substrate; and

electrically biasing said first external electrode and said second external electrode with respect to each other to induce flow of electrically charged material through said nanochannel.

4. The method of claim 3, further comprising connecting a leakage current measurement circuitry to said conductive structures, said leakage current measurement circuitry is configured to measure a leakage current through said pair of parallel electrodes and a portion of said electrically charged material within said nanochannel.

5. The method of claim 1, wherein said nanochannel is defined by a rectangular periphery having a width in a range from 0.5 nm to 100 nm, and a length L that is greater than said width, said width being perpendicular to a lengthwise direction of said semiconductor fins and said length being parallel to said lengthwise direction.

6. The method of claim 1, further comprising forming raised active regions on said pair of parallel electrodes by depositing a doped semiconductor material, wherein said nanochannel is defined by a periphery including edges of said raised active regions.

7. The method of claim 6, wherein said periphery further includes a portion of a sidewall of a dielectric material layer located within said metal interconnect structure-containing layer, said sidewall being a surface defining a lateral extent of said contiguous cavity.

8. The method of claim 6, further comprising:

forming an additional semiconductor fin on said substrate; and

forming a raised inactive region located on said additional semiconductor fin, said inactive region, including an intrinsic semiconductor material.

9. The method of claim 1, further comprising forming. at least one gate structure straddling said pair of parallel electrodes, wherein a periphery of said nanochannel includes an edge of one of said at least one gate structure.

10. The method of claim 1, wherein a portion of said contiguous cavity above said substrate is formed by etching a region of said at least one dielectric material layer over said pair of parallel electrodes such that sidewalls within said contiguous cavity vertically extend from a topmost surface of said contiguous cavity to a surface selected from a horizontal surface of said substrate and. a surface of said pair of parallel electrodes.