Physically aware insertion of diagnostic circuit elements

• US 9,557,381 B1
• Filed: 01/05/2016
• Issued: 01/31/2017
• Est. Priority Date: 01/05/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Huott, William V., Kusko, Mary P., Rangarajan, Sridhar H., Redburn, Robert C., Turner, Andrew A.
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US14/987,824
• Time in Patent Office: 392 Days
• Field of Search: 714/726
• US Class Current: 1/1
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

According to an embodiment of the present invention, a computer-implemented method for inserting diagnostic circuit elements in a scan chain of a chip may include creating, via a processor, a segment for each latch of a plurality of latches in the scan chain to create a plurality of adjacent and connected segments, merging, via the processor, the two adjacent and connected segments to form a super-segment comprising all latches contained in the two adjacent and connected segments based on the objective function, and inserting, via the processor, a logic circuit element between the super-segment and a segment that is adjacent and connected to the super-segment in the scan chain, where the logic circuit element allows diagnostic isolation of the scan chain super-segment.

Claims

1. A computer-implemented method for inserting diagnostic circuit elements in a scan chain of a chip comprising:

creating, via a processor, a segment for each latch of a plurality of latches in the scan chain to create a plurality of adjacent and connected segments;

merging, via the processor, the two adjacent and connected segments to form a super-segment comprising all latches contained in the two adjacent and connected segments based on an objective function, wherein the objective function comprises a predetermined rule;

analyzing a placement of the segment to identify two adjacent segments that satisfy the objective function comprises;

selecting, via the processor, at least one parameter from a plurality of parameters associated with the objective function;

determining, via the processor, a weighted value for each of the at least one parameter;

defining an aggregate parameter threshold value; and

determining, via the processor, whether a sum of the weighted values for the at least one parameter is greater than the aggregate parameter threshold value; and

inserting, via the processor, a logic circuit element between the super-segment and a segment that is adjacent and connected to the super-segment in the scan chain, wherein the logic circuit element allows diagnostic isolation of the scan chain super-segment.

2. The computer-implemented method of claim 1, comprising identifying, via the processor, two adjacent and connected segments that optimally satisfy an objective function by determining a local minima and maxima across the scan chain.

3. The computer-implemented method of claim 1, comprising identifying, via the processer, a next adjacent and connected segment that satisfies an objective function.

4. The computer-implemented method of claim 1, further comprising:

determining, via the processor, whether a predetermined rule is broken; and

responsive to determining that the predetermined rule is not broken, inserting the logic circuit element between the super-segment and the segment that is adjacent and connected to the super-segment.

5. The computer-implemented method of claim 1, wherein the plurality of parameters for optimizing the objective function comprises a segment area.

6. The computer-implemented method of claim 1, wherein the plurality of parameters for optimizing the objective function comprises an area by metal level.

7. The computer-implemented method of claim 1, wherein the plurality of parameters for optimizing the objective function comprises a maximum wire length.

8. The computer-implemented method of claim 1, wherein the plurality of parameters for optimizing the objective function comprises a maximum count of elements.

9. The computer-implemented method of claim 1, wherein the plurality of parameters for optimizing the objective function comprises a total iteration count.

10. A system for inserting diagnostic circuit elements on a scan chain of a chip comprising:

a processor configured to;

create a segment for each latch of a plurality of latches in the scan chain to create a plurality of adjacent and connected segments;

merge the two adjacent and connected segments based on an objective function to form a super-segment comprising all latches contained in the two adjacent and connected segments, wherein the objective function comprises a predetermined rule;

select at least one parameter from a plurality of parameters associated with the objective function;

determine a weighted value for each of the at least one parameter;

define an aggregate parameter threshold value; and

determine whether a sum of the weighted values for the at least one parameter is greater than the aggregate parameter threshold value; and

analyze a placement of the segment to identify two adjacent segments that satisfy the objective function; and

insert a logic circuit element between the super-segment and a segment that is adjacent and connected to the super-segment in the scan chain, wherein the logic circuit element allows diagnostic isolation of a scan chain super-segment.

11. The system of claim 10, comprising identifying, via the processor, two adjacent and connected segments that optimally satisfy an objective function by determining a local minima and maxima across the scan chain.

12. The system of claim 10, comprising identifying, via the processer, a next adjacent and connected segment that satisfies an objective function.

13. The system of claim 10, wherein the processor is configured to:

determine whether a predetermined rule is broken; and

responsive to determining that the predetermined rule is not broken, insert the logic circuit element between the super-segment and the segment that is adjacent and connected to the super-segment.

14. The system of claim 10, wherein the plurality of parameters for optimizing the objective function comprises a segment area.

15. The system of claim 10, wherein the plurality of parameters for optimizing the objective function comprises an area by metal level.

16. The system of claim 10, wherein the plurality of parameters for optimizing the objective function comprises one or more of a maximum wire length, a maximum count of elements and a total iteration count.

17. A non-transitory computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method for inserting diagnostic circuit elements on a scan chain of a chip, the method comprising:

creating, via the processor, a segment for each latch of a plurality of latches in the scan chain to create a plurality of adjacent and connected segments;

merging, via the processor, the two adjacent and connected segments to form a super-segment comprising all latches contained in the two adjacent and connected segments based on an objective function, wherein the objective function comprises a predetermined rule;

analyzing a placement of the segment to identify two adjacent segments that satisfy the objective function comprises;

selecting, via the processor, at least one parameter from a plurality of parameters associated with the objective function;

determining, via the processor, a weighted value for each of the at least one parameter;

defining an aggregate parameter threshold value; and

determining, via the processor, whether a sum of the weighted values for the at least one parameter is greater than the aggregate parameter threshold value;

grouping latches based on a timing element type; and

inserting, via the processor, a logic circuit between the super-segment and a segment that is adjacent and connected to the super-segment in the scan chain, wherein the logic circuit allows diagnostic isolation of the scan chain super-segment.

18. The non-transitory computer-readable storage medium of claim 17, further comprising:

determining, via the processor, whether a predetermined rule is broken; and

responsive to determining that the predetermined rule is not broken, inserting the logic circuit element between the super-segment and the segment that is adjacent and connected to the super-segment.