Configurable logic constructs in a loop buffer

• US 9,557,997 B2
• Filed: 07/22/2013
• Issued: 01/31/2017
• Est. Priority Date: 10/02/2012
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Basant, Aarti, Gold, Brian, Schlanger, Erik
• Primary Examiner(s): TSENG, CHENG YUAN
• Application Number:
  US13/947,674
• Publication Number:
  US 20150026434A1
• Time in Patent Office: 1,289 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/082 Associative directories G06F12/0822 takes precedence
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 12/1475 in a virtual system, e.g. with translation means
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/17331 Distributed shared memory [DSM], e.g. remote direct memory access [RDMA]
• CPC Class Codes: G06F 15/7889 Reconfigurable logic implemented as a co-processor instruction execution using a coprocessor G06F9/3877
• CPC Class Codes: G06F 16/2237 Vectors, bitmaps or matrices
• CPC Class Codes: G06F 16/2453 Query optimisation
• CPC Class Codes: G06F 16/24553 of query operations
• CPC Class Codes: G06F 16/24558 Binary matching operations
• CPC Class Codes: G06F 16/2456 Join operations
• CPC Class Codes: G06F 16/24561 Intermediate data storage techniques for performance improvement
• CPC Class Codes: G06F 16/24569 Query processing with adaptation to specific hardware, e.g. adapted for using GPUs or SSDs
• CPC Class Codes: G06F 16/273 Asynchronous replication or reconciliation
• CPC Class Codes: G06F 16/284 Relational databases
• CPC Class Codes: G06F 16/9535 Search customisation based on user profiles and personalisation
• CPC Class Codes: G06F 21/6209 : to a single file or object, e.g. in a secure envelope, encrypted and accessed using a key, or with access control rules appended to the object itself
• CPC Class Codes: G06F 9/30065 : Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/381 : Loop buffering
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/546 : Message passing systems or structures, e.g. queues
• CPC Class Codes: H04L 69/14 : Multichannel or multilink protocols
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques are described herein for using configurable logic constructs in a loop buffer. In an embodiment, a configurable hardware block is programmed based on one or more target functions within a loop. The configurable hardware block is associated with a plurality of registers, including a loopcount register and a first output register. For each iteration of the loop, a counter value in the loopcount register is updated and a target value in the first output register is updated using the programmed configurable hardware block. For each iteration of the loop, a set of one or more instructions may be fetched from the instruction buffer and executed based on the updated target value in the first output value.

Claims

1. A method for executing a loop on a computing system, the method comprising:

programming, into hardware of a configurable hardware block, a hardware circuit that performs one or more target functions within the loop, wherein programming reconfigures one or more of;

a programmable interconnect to change how a plurality of logic blocks are connected,

a lookup table, for a particular logic block, to change the output of the particular logic block for a given input, and

a plurality of multiplexors and based on a particular value for a set of bits of a pre-defined plurality of acceptable values for the set of bits, wherein each value of the plurality of acceptable values designates a particular configuration of a pre-defined plurality of configurations of the plurality of multiplexors;

wherein the configurable hardware block is associated with a plurality of registers;

wherein the plurality of registers includes a loopcount register, an input register and an output register;

for each iteration of the loop,

(a) updating, in the loopcount register, a counter value that tracks a number of iterations in the loop; and

(b) updating a target value in the output register based at least in part by loading a value from the input register into the hardware circuit of the programmed configurable hardware block.

2. The method of claim 1, further comprising:

storing a set of one or more instructions within the loop in an instruction buffer;

for each iteration of the loop,

(a) fetching the set of one or more instructions from the instruction buffer; and

(b) executing the set of one or more instructions based on the updated target value in the output register.

3. The method of claim 2, further comprising:

determining, based on the counter value, that a program flow should exit the loop;

in response to determining, based on the counter value, that the program flow should exit the loop, fetching a subsequent instruction in the program flow from a different location than the instruction buffer.

4. The method of claim 1, wherein the input register is the loopcount register.

5. The method of claim 1, wherein the input register provides at least one input value to the programmed configurable hardware block for each iteration of the loop.

6. The method of claim 1, wherein each register of the plurality of registers is a general purpose register (GPR) of a central processing unit (CPU) within the computing system;

wherein updating, in the output register, a target value using the programmed configurable hardware block comprises updating the respective GPR.

7. The method of claim 1, wherein the plurality of registers further includes a second output register, the method further comprising updating, in the second output register, a second target value using the programmed configurable hardware block.

8. The method of claim 7, wherein the second target value is updated, based at least in part, on the value in the input register.

9. The method of claim 1, wherein programming a configurable hardware block based on one or more target functions within the loop comprises forming a tree of operators that are executed for each loop iteration;

wherein the output of a first operator in the tree is used as input to a second operator in the tree.

28. The method of claim 1 wherein a memory-mapped register comprises said set of bits.

29. The method of claim 1 wherein reconfigures the programmable interconnect to change how the plurality of logic blocks are connected comprises reconfigures based on a bit-stream that specifies a configuration of said hardware circuit.

30. The method of claim 29 wherein reconfigures based on a bit-stream comprises receiving a central processing unit (CPU) instruction that references said bit-stream.

10. One or more non-transitory computer-readable media storing instructions for executing a loop on a computer system, the instructions, in response to being executed by one or more processors, causing the computing system to perform operations comprising:

programming, into hardware of a configurable hardware block, a hardware circuit that performs one or more target functions within the loop, wherein programming reconfigures one or more of;

a programmable interconnect to change how a plurality of logic blocks are connected,

a lookup table, for a particular logic block, to change the output of the particular logic block for a given input, and

a plurality of multiplexors and based on a particular value for a set of bits of a pre-defined plurality of acceptable values for the set of bits, wherein each value of the plurality of acceptable values designates a particular configuration of a pre-defined plurality of configurations of the plurality of multiplexors;

wherein the configurable hardware block is associated with a plurality of registers;

wherein the plurality of registers includes a loopcount register, an input register and an output register;

for each iteration of the loop,

(a) updating, in the loopcount register, a counter value that tracks a number of iterations in the loop; and

(b) updating a target value in the output register based at least in part by loading a value from the input register into the hardware circuit of the programmed configurable hardware block.

11. The non-transitory computer-readable media of claim 10, wherein the instructions further cause operations comprising:

storing a set of one or more instructions within the loop in an instruction buffer;

for each iteration of the loop,

(a) fetching the set of one or more instructions from the instruction buffer; and

(b) executing the set of one or more instructions based on the updated target value in the output register.

12. The non-transitory computer-readable media of claim 11, wherein the instructions further cause operations comprising:

determining, based on the counter value, that a program flow should exit the loop;

in response to determining, based on the counter value, that the program flow should exit the loop, fetching a subsequent instruction in the program flow from a different location than the instruction buffer.

13. The non-transitory computer-readable media of claim 10, wherein the input register is the loopcount register.

14. The non-transitory computer-readable media of claim 10, wherein the instructions cause the input register to provide at least one input value to the programmed configurable hardware block for each iteration of the loop.

15. The non-transitory computer-readable media of claim 10, wherein each register of the plurality of registers is a general purpose register (GPR) of a central processing unit (CPU) within the computing system;

wherein instructions for updating, in the output register, a target value using the programmed configurable hardware block comprise instructions for updating the respective GPR.

16. The non-transitory computer-readable media of claim 10, wherein the plurality of registers further includes a second output register, the instructions further causing operations comprising updating, in the second output register, a second target value using the programmed configurable hardware block.

17. The non-transitory computer-readable media of claim 16, wherein the second target value is updated, based at least in part, on the value in the input register.

18. The non-transitory computer-readable media of claim 10, wherein instructions for programming a configurable hardware block based on one or more target functions within the loop comprises instructions for forming a tree of operators that are executed for each loop iteration;

wherein the output of a first operator in the tree is used as input to a second operator in the tree.

19. A system for executing a loop, the system comprising:

one or more processors;

a configurable hardware block that is programmable by the one or more processors;

wherein the configurable hardware block is associated with a plurality of registers;

wherein the plurality of registers includes a loopcount register, an input register, and an output register;

one or more non-transitory computer-readable media storing instructions which, in response to being executed by the one or more processors, cause operations comprising;

programming, into hardware of a configurable hardware block, a hardware circuit that performs one or more target functions within the loop, wherein programming reconfigures one or more of;

a programmable interconnect to change how a plurality of logic blocks are connected,

a lookup table, for a particular logic block, to change the output of the particular logic block for a given input, and

a plurality of multiplexors and based on a particular value for a set of bits of a pre-defined plurality of acceptable values for the set of bits, wherein each value of the plurality of acceptable values designates a particular configuration of a pre-defined plurality of configurations of the plurality of multiplexors;

for each iteration of the loop,

(a) updating, in the loopcount register, a counter value that tracks a number of iterations in the loop; and

(b) updating a target value in the output register based at least in part by loading a value from the input register into the hardware circuit of the programmed configurable hardware block.

20. The system of claim 19, further comprising:

an instruction buffer;

wherein the instructions further cause operations comprising;

storing a set of one or more instructions within the loop in the instruction buffer;

for each iteration of the loop,

(a) fetching the set of one or more instructions from the instruction buffer; and

(b) executing the set of one or more instructions based on the updated target value in the output register.

21. The system of claim 20, wherein the instructions further cause operations comprising:

determining, based on the counter value, that a program flow should exit the loop;

in response to determining, based on the counter value, that the program flow should exit the loop, fetching a subsequent instruction in the program flow from a different location than the instruction buffer.

22. The system of claim 19, wherein the input register is the loopcount register.

23. The system of claim 19, wherein the instructions cause the input register to provide at least one input value to the programmed configurable hardware block for each iteration of the loop.

24. The system of claim 19, wherein each register of the plurality of registers is a general purpose register (GPR) of a processor of the one or more processors;

wherein instructions for updating, in the output register, a target value using the programmed configurable hardware block comprise instructions for updating the respective GPR.

25. The system of claim 19 wherein the plurality of registers further includes a second output register, the instructions further causing operations comprising updating, in the second output register, a second target value using the programmed configurable hardware block.

26. The system of claim 25 wherein the second target value is updated, based at least in part, on the value in the input register.

27. The system of claim 19 wherein instructions for programming a configurable hardware block based on one or more target functions within the loop comprises instructions for forming a tree of operators that are executed for each loop iteration;

wherein the output of a first operator in the tree is used as input to a second operator in the tree.