Non-intrusive monitoring and control of integrated circuits

• US 9,558,090 B2
• Filed: 08/12/2015
• Issued: 01/31/2017
• Est. Priority Date: 07/04/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Olgiati, Andrea, Baker, Matthew Pond, Teig, Steven
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US14/824,368
• Publication Number:
  US 20150347257A1
• Time in Patent Office: 538 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/3003 Monitoring arrangements specially adapted to the computing system or computing system component being monitored
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Claims

1. An integrated circuit, comprising:

a plurality of reconfigurable circuits that performs custom operations based on configuration data; and

a configuration and monitoring network that monitors a set of signals associated with the plurality of reconfigurable circuits based on incremental configuration data that is at least in part different than the configuration data.

2. The integrated circuit defined in claim 1, wherein the incremental configuration data configures the configuration and monitoring network to take corresponding actions in response to the monitored set of signals satisfying a set of predetermined conditions.

3. The integrated circuit defined in claim 1, wherein the incremental configuration data configures the configuration and monitoring network without interrupting the custom operations that is being performed by the plurality of reconfigurable circuits.

4. The integrated circuit defined in claim 1, further comprising:

a plurality of non-configurable circuits that outputs the set of signals to the plurality of reconfigurable circuits.

5. The integrated circuit defined in claim 1, wherein the configuration and monitoring network receives the incremental configuration data from an external computing device.

6. The integrated circuit defined in claim 1, further comprising:

a controller that outputs the incremental configuration data to the configuration and monitoring network.

7. The integrated circuit defined in claim 1, wherein the configuration and monitoring network performs root cause analysis.

8. The integrated circuit defined in claim 1, wherein the configuration and monitoring network intentionally injects a fault into the integrated circuit.

9. The integrated circuit defined in claim 1, wherein the configuration and monitoring network inspects and searches for particular network packets.

10. A method for operating an integrated circuit that includes reconfigurable circuits, comprising:

configuring the reconfigurable circuits to perform custom operations by loading configuration data into the integrated circuit; and

while the reconfigurable circuits are performing the custom operations, reconfiguring a configuration and monitoring network on the integrated circuit to monitor for an event by loading an overlay that includes additional configuration data.

11. The method defined in claim 10, further comprising:

in response to detecting the event, performing corresponding actions.

12. The method defined in claim 11, wherein performing the corresponding actions comprises collecting and storing data in storage circuitry on the integrated circuit.

13. The method defined in claim 11, wherein performing the corresponding actions comprises sending data to a specified destination on the integrated circuit.

14. The method defined in claim 11, wherein performing the corresponding actions comprises sending data to a component that is external to the integrated circuit.

15. The method defined in claim 11, wherein performing the corresponding actions comprises reconfiguring at least a portion of the reconfigurable circuits.

16. A method of operating an integrated circuit having configurable circuits for implementing a custom user design, the method comprising:

configuring the configurable circuits by loading configuration data into the integrated circuit;

receiving a definition of an event and a set of actions to take in response to detecting the event; and

generating additional configuration data based on the definition of the event and the set of actions.

17. The method defined in claim 16, further comprising:

while the configurable circuits is performing the custom user design, loading the additional configuration data into the integrated circuit that enables the integrated circuit to monitor for the event.

18. The method defined in claim 17, further comprising:

after the additional configuration data has been loaded into the integrated circuit, taking the set of actions in response to detecting the event.

19. The method defined in claim 17, further comprising:

using a configuration and monitoring network on the integrated circuit to receive the additional configuration data, to monitoring for the event, and to take the set of actions in response to detecting the event.

20. The method defined in claim 16, further comprising:

receiving a definition of an additional event and a set of actions to take in response to detecting the additional event;

generating incremental configuration data based on the definition of the additional event and the associated set of actions; and

while the configurable circuits is performing the custom user design, loading the incremental configuration data into the integrated circuit that enables the integrated circuit to monitor for the additional event.