Half block management for flash storage devices
First Claim
Patent Images
1. An operating method for a memory, comprising:
- maintaining, for an array of memory cells including erasable blocks of memory cells in the array, status data for a plurality of sub-blocks of the erasable blocks, the status data indicating whether the sub-blocks are currently accessible and whether the sub-blocks are invalid; and
in response to a request to erase a selected sub-block of a particular erasable block;
determining the status data of the other sub-block or sub-blocks in the particular erasable block, and updating the status data of the selected sub-block to indicate a changed status if the status data of fewer than a pre-determined number of the other sub-block or sub-blocks of the particular erasable block indicates a same status as the changed status, and issuing an erase command to erase the particular erasable block if the status data indicate the pre-determined number of the other sub-block or sub-blocks of the particular erasable blocks is/are invalid, else the changed status of updating the status data to indicate that the selected sub-block is invalid.
1 Assignment
0 Petitions
Accused Products
Abstract
A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.
5 Citations
17 Claims
-
1. An operating method for a memory, comprising:
maintaining, for an array of memory cells including erasable blocks of memory cells in the array, status data for a plurality of sub-blocks of the erasable blocks, the status data indicating whether the sub-blocks are currently accessible and whether the sub-blocks are invalid; and
in response to a request to erase a selected sub-block of a particular erasable block;
determining the status data of the other sub-block or sub-blocks in the particular erasable block, and updating the status data of the selected sub-block to indicate a changed status if the status data of fewer than a pre-determined number of the other sub-block or sub-blocks of the particular erasable block indicates a same status as the changed status, and issuing an erase command to erase the particular erasable block if the status data indicate the pre-determined number of the other sub-block or sub-blocks of the particular erasable blocks is/are invalid, else the changed status of updating the status data to indicate that the selected sub-block is invalid.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
9. A memory apparatus comprising:
- computer-readable non-transitory memory storing software executable to;
maintain, for an array of memory cells including erasable blocks of memory cells in the array, status data for a plurality of sub-blocks of the erasable blocks, the status data indicating whether the sub-blocks are currently accessible and whether the sub-blocks are invalid; and
in response to a request to erase a selected sub-block of a particular erasable block;
determine the status data of the other sub-block or sub-blocks in the particular erasable block, and update the status data of the selected sub-block to indicate a changed status if the status data of fewer than a pre-determined number of the other sub-block or sub-blocks of the particular erasable block indicates a same status as the changed status, and issue an erase command to erase the particular erasable block if the status data indicate the predetermined number of the other sub-block or sub-blocks of the particular erasable blocks is/are invalid, else the changed status of updating the status data to indicate that the selected sub-block is invalid. - View Dependent Claims (10, 11)
- computer-readable non-transitory memory storing software executable to;
-
12. An apparatus comprising:
- an array of memory cells including erasable blocks of memory cells in the array; and
a processor coupled to the array, including logic to;
maintain status data for a plurality of sub-blocks of the erasable blocks, the status data indicating whether the sub-blocks are currently accessible and whether the sub-blocks are invalid; and
in response to a request to erase a selected sub-block of a particular erasable block;
determine the status data of the other sub-block or sub-blocks in the particular erasable block, and update the status data of the selected sub-block to indicate a changed status if the status data of fewer than a pre-determined number of the other sub-block or sub-blocks of the particular erasable block indicates a same status as the changed status, and issue an erase command to erase the particular erasable block if the status data indicate the predetermined number of the other sub-block or sub-blocks of the particular erasable blocks is/are invalid, else update the status data to indicate that the changed status of the selected sub-block is invalid. - View Dependent Claims (13, 14, 15, 16, 17)
- an array of memory cells including erasable blocks of memory cells in the array; and
Specification