Circuits for and methods of enabling the access to data

• US 9,558,129 B2
• Filed: 06/10/2014
• Issued: 01/31/2017
• Est. Priority Date: 06/10/2014
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Arbel, Ygal, Murray, James J., Kwon, Hyun W., Patel, Nishit
• Primary Examiner(s): Dang, Khanh
• Application Number:
  US14/301,008
• Publication Number:
  US 20150356027A1
• Time in Patent Office: 966 Days
• Field of Search: 710/22, 710/23, 710/33, 710/35, 710/105, 710/305, 710/308
• US Class Current: 1/1
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/30 with priority control

Abstract

A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed.

Claims

1. A circuit for enabling access to data, the circuit comprising:

a memory device storing data blocks having a first predetermined size;

a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size. wherein the second predetermined size of the payload data comprises a multiple N of the first predetermined size of the data blocks;

wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device; and

wherein the plurality of addresses comprises N+1 addresses and each data block other than a first data block and a last data block of the plurality of data blocks are boundary restricted.

2. The circuit of claim 1 wherein the plurality of addresses is located in a corresponding predetermined number of fields of the descriptor.

3. The circuit of claim 1 wherein the plurality of addresses comprises a memory map table to the memory device.

4. The circuit of claim 1 wherein the descriptor comprises a field having a next descriptor.

5. A circuit for enabling access to data, the circuit comprising:

a memory device storing data blocks having a first predetermined size;

a display port direct memory access circuit coupled to the memory device, the display port direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size and comprising a predetermined portion of data to be displayed, wherein the second predetermined size of the payload data comprises a multiple N of the first predetermined size of the data blocks;

a display port coupled to the display port direct memory access circuit, the display port generating the payload data;

wherein the display port direct memory access circuit accesses the data payload stored in the memory device in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device, wherein the plurality of addresses comprises N+1 addresses and each data block other than a first data block and a last data block of the plurality of data blocks are boundary restricted.

6. The circuit of claim 5 wherein the plurality of addresses is located in a predetermined number of fields of the descriptor.

7. The circuit of claim 5 wherein the plurality of addresses comprises a memory map table to the memory device.

8. The circuit of claim 5 wherein the descriptor comprises a field having a next descriptor.

9. A method of enabling access to data, the method comprising:

storing data blocks having a first predetermined size in a memory device;

receiving, at a direct memory access circuit, a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device, wherein storing the plurality of addresses comprises storing N+1 addresses;

accessing, in response to a descriptor, a data payload having the predetermined number of the data blocks corresponding to the plurality of address;

implementing a payload data size which comprises a multiple N of the first predetermined size of the data blocks; and

providing boundary restrictions for each data block other than a first data block and a last data block of the plurality of data blocks.

10. The method of claim 9 further comprising storing the plurality of addresses in a corresponding predetermined number of fields of the descriptor.

11. The method of claim 9 wherein storing the plurality of addresses comprises storing a memory map table to the memory device.