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System interconnect dynamic scaling handshake using spare bit-lane

  • US 9,558,139 B2
  • Filed: 08/18/2014
  • Issued: 01/31/2017
  • Est. Priority Date: 08/18/2014
  • Status: Expired due to Fees
First Claim
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1. A communications interface for connecting processing units within a computer system, the interface comprising:

  • a first physical link layer within a first one of the processing units and comprising a first transceiver and a first control circuit;

    a second physical link layer within a second one of the processing units and comprising a second transceiver and a second control circuit;

    a plurality of bit-lanes connecting the first transceiver of the first physical link layer transceiver and the second transceiver of the second physical link layer, wherein the first control circuit changes at least one of a first active width or a first operating frequency of first transceiver to at least one of a second active width or a second operating frequency and communicates an indication of the at least one of the second active width or the second operating frequency to the second control circuit over a spare bit lane of the interface, wherein the spare bit lane is a lane that is not in use for the communicating of data between the first physical link layer and the second physical link layer, and wherein the second control circuit receives the indication, and in response, changes at least one of an active width or an operating frequency of the second transceiver to the at least one of the second width or the second operating frequency and communicates an acknowledgement to the first control circuit that indicates that the second transceiver is operating with the at least one of the second width or the second operating frequency as changed in response to receiving the indication, wherein subsequent to the second control circuit changing the second active width of the interface, the interface has a current active width less than a maximum active width of the interface, whereby one or more bit-lanes are disabled, and wherein the second control circuit uses the one or more disabled lanes of the interface to communicate the acknowledgement, whereby the indication is communicated over the spare bit-lane, but the acknowledgement is not communicated over the spare bit-lane.

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