Method of operating incrementally programmable non-volatile memory

• US 9,558,813 B2
• Filed: 04/18/2016
• Issued: 01/31/2017
• Est. Priority Date: 08/05/2013
• Status: Active Grant

• Current Assignee: Jonker LLC
• Original Assignee: Jonker LLC
• Inventors: Liu, David K. Y.
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/131,429
• Publication Number:
  US 20160307623A1
• Time in Patent Office: 288 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a V_t representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.

Claims

1. A method of dividing a total capacity (Ct) of an non-volatile memory array containing M cells and N distinct program levels into P distinct periods, the method comprising:

performing a first program operation in a first period of the P distinct periods to store logical data in the M cells of the array using at least two or more separate program levels {PVt1, PVt2} of the N distinct program levels; and

performing a second program operation in a subsequent second period of the P distinct periods to store logical data in the M cells of the array using at least two separate program levels {PVt3, PVt4} of the N distinct program levels, wherein at least one of {PVt3, PVt4} is different from and greater than {PVt1, PVt2};

wherein data in the M cells is reset to a common initialized state by a reset operation between the first and second program operations.

2. The method of claim 1, wherein the array is erased between program operations by adding charge to a floating gate of each of the M cells to achieve said reset operation.

3. The method of claim 2, wherein a threshold value of programmed cells is increased during each subsequent program operation in the P distinct periods.

4. The method of claim 1, wherein a total capacity of Ct is time multiplexed into an available capacity Ca =Ct/P at any moment in time.

5. The method of claim 1, wherein the M cells store a multi-bit logic value during at least one of the P distinct periods.

6. A method of dividing a total capacity (Ct) of an non-volatile memory array containing M cells and N distinct program levels into P distinct periods, the method comprising:

performing a first program operation in a first period of the P distinct periods to store logical data in the M cells of the array using at least two or more separate program levels {PVt1, PVt2} of the N distinct program levels; and

performing a second program operation in a subsequent second period of the P distinct periods to store logical data in the M cells of the array using at least two separate program levels {PVt3, PVt4} of the N distinct program levels, wherein at least one of {PVt3, PVt4} is different from and greater than {PVt1, PVt2};

wherein said first program operation and said second program operation utilize charge storage to set a value of said logical data;

further wherein data in the M cells is reset to a common initialized state by a reset operation between the first and second program operations, which reset operation does not remove charge from said cells.

7. The method of claim 6, wherein each of the M cells in the array implements a multi-time programmable (MTP) cell by programming a one-time-programmable (OTP) cell once in each programming operation for multiple program operations.

8. The method of claim 6, wherein at least one of said first program operation and said second program operation stores a data item having more than two logical values.

9. The method of claim 6, wherein said second program operation is performed automatically for the array at a predetermined time interval.

10. The method of claim 6, wherein said second program operation is performed automatically for the array in response to detecting degradation of threshold values from said first program operation.

11. The method of claim 6, wherein a reference cell used for a read operation after said first program operation is changed for read operations performed after said second program operation.

12. The method of claim 6, wherein said charge storage is effectuated by channel hot electron injection to a floating gate.