Sampling network and clocking scheme for a switched-capacitor integrator
First Claim
Patent Images
1. A switched-capacitor integrator, comprising:
- an amplifier having first and second output nodes and first and second input nodes;
a first integration capacitor coupled between the first output node and the first input node of the amplifier;
a second integration capacitor coupled between the second output node and the second input node of the amplifier;
first and second sampling capacitors, each having a first terminal and a second terminal;
a first set of switches configured, during a first sampling phase of the integrator, to connect first and second voltages of a differential signal with the first terminals of the first and second sampling capacitors, respectively;
a second set of switches configured to connect the second terminals of the first and second sampling capacitors with a reference potential during the first sampling phase of the integrator, wherein a switching frequency of the first set of switches is less than a switching frequency of the second set of switches; and
a third set of switches configured, during a first integration phase of the integrator, to connect the second terminals of the first and second sampling capacitors with the first and second input nodes of the amplifier, respectively.
1 Assignment
0 Petitions
Accused Products
Abstract
Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.
-
Citations
30 Claims
-
1. A switched-capacitor integrator, comprising:
-
an amplifier having first and second output nodes and first and second input nodes; a first integration capacitor coupled between the first output node and the first input node of the amplifier; a second integration capacitor coupled between the second output node and the second input node of the amplifier; first and second sampling capacitors, each having a first terminal and a second terminal; a first set of switches configured, during a first sampling phase of the integrator, to connect first and second voltages of a differential signal with the first terminals of the first and second sampling capacitors, respectively; a second set of switches configured to connect the second terminals of the first and second sampling capacitors with a reference potential during the first sampling phase of the integrator, wherein a switching frequency of the first set of switches is less than a switching frequency of the second set of switches; and a third set of switches configured, during a first integration phase of the integrator, to connect the second terminals of the first and second sampling capacitors with the first and second input nodes of the amplifier, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A method for processing a differential signal with a switched-capacitor integrator, comprising:
-
during a first sampling phase of the integrator, sampling first and second voltages of a differential signal via first and second sampling capacitors, each having a first terminal and a second terminal, wherein the sampling comprises; connecting, via a first set of switches, the first and second voltages of the differential signal with the first terminals of the first and second sampling capacitors, respectively; and connecting, via a second set of switches, the second terminals of the first and second sampling capacitors with a reference potential, wherein a switching frequency of the first set of switches is less than a switching frequency of the second set of switches; and during a first integration phase of the integrator, integrating the sampled first and second voltages of the differential signal, via an amplifier having first and second input nodes and first and second output nodes, wherein a first integration capacitor is coupled between the first output node and the first input node of the amplifier, wherein a second integration capacitor is coupled between the second output node and the second input node of the amplifier, and wherein the integrating comprises connecting, via a third set of switches, the second terminals of the first and second sampling capacitors with the first and second input nodes of the amplifier, respectively. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
-
Specification