Methods for making a semiconductor device including atomic layer structures using N;O as an oxygen source

• US 9,558,939 B1
• Filed: 01/15/2016
• Issued: 01/31/2017
• Est. Priority Date: 01/15/2016
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Stephenson, Robert, Cody, Nyles
• Primary Examiner(s): Nguyen, Thanh T
• Application Number:
  US14/996,312
• Time in Patent Office: 382 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

A method for making a semiconductor device may include forming a plurality of spaced apart structures on a semiconductor substrate within a semiconductor processing chamber, with each structure including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. Furthermore, the oxygen monolayers may be formed using N₂O as an oxygen source.

Claims

1. A method for making a semiconductor device comprising:

forming a plurality of spaced apart structures on a semiconductor substrate within a semiconductor processing chamber, each structure comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

wherein the oxygen monolayers are formed using N₂O as an oxygen source.

2. The method of claim 1 wherein forming comprises forming the plurality of groups of spaced apart structures using epitaxial chemical vapor deposition (CVD).

3. The method of claim 1 wherein the base silicon monolayers are formed at a temperature in a range of 600°

C. to 800°

C.

4. The method of claim 3 wherein the base silicon monolayers are formed at a temperature in a range of 665°

C. to 685°

C.

5. The method of claim 1 wherein the oxygen monolayers are formed at a temperature in a range of 500°

C. to 750°

C.

6. The method of claim 1 wherein an exposure time for the oxygen source is between 1 and 240 seconds.

7. The method of claim 1 wherein the oxygen source comprises a helium source gas with less than 2% N₂O.

8. The method of claim 1 further comprising forming shallow trench isolation (STI) regions between the spaced apart structures.

9. The method of claim 8 wherein the STI regions are formed prior to forming the spaced apart structures.

10. The method of claim 1 further comprising forming a respective cap semiconductor layer on each of the spaced apart structures.

11. The method of claim 10 wherein forming the cap semiconductor layers comprises forming the cap semiconductor layers at a temperature in a range of 580°

C. to 900°

C.

12. A method for making a semiconductor device comprising:

forming a plurality of spaced apart structures on a semiconductor substrate with shallow trench isolation (STI) regions between adjacent structures within a semiconductor processing chamber using epitaxial chemical vapor deposition (CVD), each structure comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

wherein the oxygen monolayers are formed using N₂O as an oxygen source.

13. The method of claim 12 wherein the base silicon monolayers are formed at a temperature in a range of 600°

C. to 800°

C.

14. The method of claim 13 wherein the base silicon monolayers are formed at a temperature in a range of 665°

C. to 685°

C.

15. The method of claim 12 wherein the oxygen monolayers are formed at a temperature in a range of 500°

C. to 750°

C.

16. The method of claim 12 wherein an exposure time for the oxygen source is between 1 and 240 seconds.

17. The method of claim 12 wherein the oxygen source comprises a helium source gas with less than 2% N₂O.

18. The method of claim 12 wherein the STI regions are formed prior to forming the spaced apart structures.

19. The method of claim 12 further comprising forming a respective cap semiconductor layer on each of the spaced apart structures.

20. The method of claim 12 wherein forming the cap semiconductor layers comprises forming the cap semiconductor layers at a temperature in a range of 580°

C. to 900°

C.

21. A method for making a semiconductor device comprising:

forming a plurality of spaced apart structures on a semiconductor substrate within a semiconductor processing chamber, each structure comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

wherein the oxygen monolayers are formed using N₂O as an oxygen source at a temperature in a range of 500°

C. to 750°

C., and wherein the base silicon monolayers are formed at a temperature in a range of 600°

C. to 800°

C.

22. The method of claim 21 wherein forming comprises forming the plurality of groups of spaced apart structures using epitaxial chemical vapor deposition (CVD).

23. The method of claim 21 wherein the base silicon monolayers are formed at a temperature in a range of 665°

C. to 685°

C.

24. The method of claim 21 wherein an exposure time for the oxygen source is between 1 and 240 seconds.

25. The method of claim 21 wherein the oxygen source comprises a helium source gas with less than 2% N₂O.