Three-dimensional semiconductor architecture

• US 9,559,003 B2
• Filed: 08/17/2015
• Issued: 01/31/2017
• Est. Priority Date: 04/07/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Law, Oscar M. K., Wu, Kuo H.
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US14/827,749
• Publication Number:
  US 20150357240A1
• Time in Patent Office: 533 Days
• Field of Search: 257/774, 257/776, 257/E23.067, 257/E21.577, 438/637
• US Class Current: 1/1
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming first active devices at least partially within a first surface of a substrate, wherein the substrate comprises a second surface, an interior region, and a periphery region surrounding the interior region;

forming a first set of through substrate vias within the periphery region and extending from the first surface of the substrate to the second surface of the substrate; and

forming a second set of through substrate vias within the interior region and extending from the first surface of the substrate to the second surface of the substrate, wherein the second set of through substrate vias are part of a power matrix, the second set of through substrate vias bisecting the substrate into a first part and a second part.

2. The method of claim 1, wherein the second set of through substrate vias further bisects the first part into a third part and a fourth part.

3. The method of claim 2, wherein the third part and the fourth part are square in shape.

4. The method of claim 1, wherein the first set of through vias comprises signal vias.

5. The method of claim 1, further comprising forming at least one redistribution line located on the second surface, the at least one redistribution line electrically connecting multiple ones of the second set of through substrate vias.

6. The method of claim 1, wherein the interior region is free from signal vias.

7. The method of claim 1, wherein the second set of through vias extend through the substrate and through a second substrate, the second substrate comprising second active devices.

8. A method of manufacturing a semiconductor device, the method comprising:

forming active devices located at least partially within a first surface of a substrate, the substrate further comprising a second surface opposite the first surface;

forming a first plurality of through vias around a periphery of the substrate and extending from the first surface of the substrate to the second surface of the substrate; and

creating a set of power matrix through vias located within an interior of the substrate and extending from the first surface of the substrate to the second surface of the substrate, the interior being surrounded by the periphery, wherein the set of power matrix through vias are arranged in at least one straight line.

9. The method of claim 8, wherein the forming the first plurality of through vias comprises forming signal vias.

10. The method of claim 8, wherein the at least one straight line comprises two or more straight lines.

11. The method of claim 10, wherein at least two of the two or more straight lines are parallel with each other.

12. The method of claim 10, wherein at least two of the two or more straight lines are perpendicular with each other.

13. The method of claim 10, wherein the two or more straight lines further comprises:

a first line;

a second line perpendicular to the first line; and

a third line parallel with the first line.

14. The method of claim 8, wherein there are no signal through vias within the interior of the substrate.

15. The method of claim 8, further comprising forming at least one signal through via within the interior of the substrate.

16. A method of manufacturing a semiconductor device, the method comprising:

forming a first via last through via extending through a first semiconductor die, the first semiconductor die further comprising a first active device at least partially within a first surface of a substrate;

forming a second via last through via extending through a second semiconductor;

forming a first set of through vias extending through a periphery region of the substrate of the first semiconductor die, the through vias extending between the first surface and a second surface of the first semiconductor die; and

forming a second set of through vias extending through an interior region of the substrate between the first surface and the second surface of the first semiconductor die, the second set of through vias being a portion of a power matrix; and

bonding the first semiconductor die to the second semiconductor die, wherein after the bonding the second via last through via is in electrical connection with the first via last through via and the second set of through vias are in physical contact with a metallization layer adjacent to the first active device.

17. The method of claim 16, further comprising a second active device on a second substrate of the second semiconductor die, wherein the first active device is electrically connected to the second semiconductor die through a signal through via extending through the second substrate.

18. The method of claim 16, wherein the first via last through via is a power through via.

19. The method of claim 16, further comprising a third semiconductor die over the second semiconductor die, the third semiconductor die comprising a third via last through via extending through a third substrate, the third via last through via electrically connected to the second via last through via.

20. The method of claim 16, further comprising a third semiconductor die over the second semiconductor die, the third semiconductor die comprising a through via electrically connected to the second via last through via.