Dense arrays and charge storage devices

• US 9,559,110 B2
• Filed: 09/16/2015
• Issued: 01/31/2017
• Est. Priority Date: 08/14/2000
• Status: Expired due to Term

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Lee, Thomas H.
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US14/856,131
• Publication Number:
  US 20160079258A1
• Time in Patent Office: 503 Days
• Field of Search: 257/321, 257/324
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7391 : Gated diode structures
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7889 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/8616 : Charge trapping diodes
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/60 : Peripheral circuit regions
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 : with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.

Claims

1. A memory device comprising at least one memory cell, wherein each memory cell of the memory device comprises:

a stack including a first dielectric region, a second dielectric region that is spaced from the first dielectric region, and a charge storage region configured to trap electrical charges and contacting the first dielectric region and the second dielectric region;

a p-doped region comprising a p-doped semiconductor material and contacting a first horizontal surface of the stack; and

an n-doped region comprising an n-doped semiconductor material,

wherein;

at least one of the p-doped region and the n-doped region is in physical contact with the first dielectric region;

each memory cell of the memory device comprises a semiconductor device including a p-n junction between the p-doped region and the n-doped region;

each semiconductor device comprises a diode; and

each memory device further comprises;

an anode contact in physical contact with one of the second dielectric region of the memory device and a node of the diode of the memory device that does not contact the stack; and

a cathode contact in physical contact with another of the second dielectric region of the memory device and the node of the diode of the memory device that does not contact the stack,

wherein at least one of the p-doped region and the n-doped region is in physical contact with the first dielectric region.

2. The memory device of claim 1, further comprising a programming circuitry configured to inject electrical charges into each of the at least one charge storage region.

3. The memory device of claim 2, wherein the programming circuitry is configured to provide binary programming to each of the at least one charge storage region through a binary shift between two voltage threshold curves, each of which is given by a cell current through a respective stack as a function of a forward bias voltage applied to the respective stack depending on a programmed state of the respective memory cell.

4. The memory device of claim 2, wherein the programming circuitry is configured to provide multiple bit programming to each of the at least one charge storage region through shifts among three or more voltage threshold curves, each of which given by a cell current through a respective stack as a function of a forward bias voltage applied to the respective stack depending on a programmed state of the respective memory cell.

5. The memory device of claim 2, wherein each memory cell has a cell current therethrough as a function of a forward bias voltage applied to the respective stack depending on a programmed state of the respective memory cell, wherein the forward bias voltage has a peak at a threshold forward bias voltage as a function of the cell current.

6. The memory device of claim 5, wherein the forward bias voltage has a local minimum at a voltage that is greater than the threshold forward bias voltage as a function of the cell current.

7. The memory device of claim 2, further comprising a sensing circuitry configured to sense a state of each of the at least one memory cell by applying a forward bias voltage between a voltage of the peak in the forward bias voltage and the local minimum of the forward bias voltage during a read operation.

8. The memory device of claim 7, wherein the sensing circuitry determines the state of each of the at least one memory cell by comparing a measured current through a respective memory cell with a predetermined threshold current.

9. The memory device of claim 8, wherein the read operation that is performed on a memory cell including trapped electrical charges reinforces the trapped electrical charges during the read operation.

10. The memory device of claim 8, wherein:

the sensing circuitry identifies the state of the at least one memory cell as a state including trapped electrical charges if the measured current is greater than the predetermined threshold current; and

the sensing circuitry identifies the state of the at least one memory cell as a state not including trapped electrical charges if the measured current is less than the predetermined threshold current.

11. The memory device of claim 2, further comprising an erase circuitry configured to remove trapped electrical charges from each of the at least one charge storage region.

12. The memory device of claim 11, where the erase circuitry applied a reverse bias voltage to each memory cell that tunnels out trapped electrons in each respective charge storage region.

13. The memory device of claim 1, wherein each of the first dielectric region and the second dielectric region comprises a dielectric oxide having a thickness in a range from 1 nm to 5 nm.

14. The memory device of claim 1, wherein each charge storage region comprises a material selected from a compound of nitrogen, alumina, and silicon dioxide within insulated regions of polysilicon, and has a thickness in a range from 2 nm to 20 nm.

15. The memory device of claim 1, wherein the second dielectric region comprises a dielectric material selected from perovskites, ceramics, a diamond-like material, silicon carbide, and undoped silicon.

16. The memory device of claim 1, further comprising an erase circuitry configured to remove trapped electrical charges from each of the at least one charge storage region by applying a reverse bias through a respective p-n junction such that the respective p-n junction operates at a breakdown voltage employing a mechanism selected from avalanche breakdown, Zener breakdown, and punchthrough.

17. The memory device of claim 16, wherein the substrate is electrically floated to prevent forward biasing of the semiconductor device with respect to other portions of the semiconductor substrate.

18. The memory device of claim 1, wherein:

the stack is located on a top surface of the semiconductor substrate; and

an interface between the semiconductor device and the stack is within a horizontal plane.