Memory devices and method of fabricating same
First Claim
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1. A method comprising:
- forming a control gate structure over a substrate;
depositing a charge storage layer over the control gate structure;
depositing a memory gate layer over the charge storage layer;
applying a first etching process to the memory gate layer to form a first memory gate structure and a second memory gate structure, wherein the first memory gate structure and the second memory gate structure are formed along opposite sidewalls of the control gate structure;
removing the second memory gate structure;
applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the first memory gate structure and the control gate structure;
forming a first spacer layer over the substrate;
applying a third etching process to the first spacer layer to form a first thin spacer along a sidewall of the first memory gate structure and a second thin spacer along a sidewall of the control gate structure, wherein a top surface of the first memory gate structure is exposed after the step of applying the third etching process to the first spacer layer;
forming a top spacer over the first memory gate structure after removing a portion of the first memory gate structure; and
forming a first drain/source region adjacent to the first memory gate structure and a second drain/source region adjacent to the control gate structure.
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Abstract
A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
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Citations
20 Claims
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1. A method comprising:
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forming a control gate structure over a substrate; depositing a charge storage layer over the control gate structure; depositing a memory gate layer over the charge storage layer; applying a first etching process to the memory gate layer to form a first memory gate structure and a second memory gate structure, wherein the first memory gate structure and the second memory gate structure are formed along opposite sidewalls of the control gate structure; removing the second memory gate structure; applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the first memory gate structure and the control gate structure; forming a first spacer layer over the substrate; applying a third etching process to the first spacer layer to form a first thin spacer along a sidewall of the first memory gate structure and a second thin spacer along a sidewall of the control gate structure, wherein a top surface of the first memory gate structure is exposed after the step of applying the third etching process to the first spacer layer; forming a top spacer over the first memory gate structure after removing a portion of the first memory gate structure; and forming a first drain/source region adjacent to the first memory gate structure and a second drain/source region adjacent to the control gate structure. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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forming a control gate structure over a substrate; forming an Oxide-Nitride-Oxide layer over the control gate structure; depositing a memory gate layer over the Oxide-Nitride-Oxide layer; forming a first memory gate structure and a second memory gate structure through a first etching process, wherein the first memory gate structure and the second memory gate structure are formed along opposite sidewalls of the control gate structure; removing the second memory gate structure through a second etching process; applying a third etching process to a top oxide layer and a silicon nitride layer of the Oxide-Nitride-Oxide layer; forming a first thin spacer along a sidewall of the first memory gate structure and a second thin spacer along a sidewall of the control gate structure; applying a fourth etching process to the first memory gate structure; forming a top spacer over the first memory gate structure; and forming a first drain/source region adjacent to the first memory gate structure and a second drain/source region adjacent to the control gate structure. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method comprising:
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forming a control gate structure over a substrate, wherein the control gate structure and the substrate are separated by a gate dielectric layer; forming a silicon nitride layer over the control gate structure; depositing a memory gate layer over the silicon nitride layer; applying a first etching process to the memory gate layer to form a first memory gate structure and a second memory gate structure, wherein the first etching process is applied until a top surface of the first memory gate structure is lower than a top surface of the silicon nitride layer; applying a second etching process to the silicon nitride layer until the top surface of the silicon nitride layer is lower than the top surface of the first memory gate structure; forming a first thin spacer layer along the first memory gate structure and a second thin spacer layer along a sidewall of the control gate structure; applying a third etching process to the first memory gate structure until the top surface of the first memory gate structure is lower than the top surface of the silicon nitride layer; and forming a memory gate spacer over the first memory gate structure, wherein the memory gate spacer is in direct contact with the first memory gate structure. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification