Memory devices and method of fabricating same

• US 9,559,177 B2
• Filed: 12/03/2013
• Issued: 01/31/2017
• Est. Priority Date: 12/03/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chang-Ming, Wu, Wei Cheng, Liu, Shih-Chang, Chuang, Harry-Hak-Lay, Tsai, Chia-Shiung
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US14/095,588
• Publication Number:
  US 20150155293A1
• Time in Patent Office: 1,155 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Claims

1. A method comprising:

forming a control gate structure over a substrate;

depositing a charge storage layer over the control gate structure;

depositing a memory gate layer over the charge storage layer;

applying a first etching process to the memory gate layer to form a first memory gate structure and a second memory gate structure, wherein the first memory gate structure and the second memory gate structure are formed along opposite sidewalls of the control gate structure;

removing the second memory gate structure;

applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the first memory gate structure and the control gate structure;

forming a first spacer layer over the substrate;

applying a third etching process to the first spacer layer to form a first thin spacer along a sidewall of the first memory gate structure and a second thin spacer along a sidewall of the control gate structure, wherein a top surface of the first memory gate structure is exposed after the step of applying the third etching process to the first spacer layer;

forming a top spacer over the first memory gate structure after removing a portion of the first memory gate structure; and

forming a first drain/source region adjacent to the first memory gate structure and a second drain/source region adjacent to the control gate structure.

2. The method of claim 1, further comprising:

forming a first salicide region over the first drain/source region; and

forming a second salicide region over the second drain/source region.

3. The method of claim 1, further comprising:

depositing a gate dielectric layer over the substrate;

depositing a control gate electrode layer over the gate dielectric layer;

depositing a first hard mask layer over the control gate electrode layer;

depositing a second hard mask layer over the first hard mask layer; and

forming the control gate structure through a patterning process.

4. The method of claim 1, further comprising:

forming a first oxide layer over the substrate and the control gate structure;

forming the charge storage layer over the first oxide layer, wherein the charge storage layer is a silicon nitride layer; and

forming a second oxide layer over the charge storage layer.

5. The method of claim 1, further comprising:

after the step of applying the third etching process to the first spacer layer to form the first thin spacer along a sidewall of the first memory gate structure and the second thin spacer along a sidewall of the control gate structure, applying a fourth etching process to the memory gate layer.

6. The method of claim 5, wherein:

the fourth etching process is an isotropic dry etching process.

7. The method of claim 1, further comprising:

forming an etch stop layer over the first memory gate structure and the control gate structure;

depositing an inter-layer dielectric layer over the etch stop layer, wherein the first memory gate structure and the control gate structure are embedded in the inter-layer dielectric layer;

performing a chemical mechanical polishing process on the inter-layer dielectric layer until a top surface of the control gate structure is exposed; and

forming contact plugs coupled to the first drain/source region and the second drain/source region.

8. A method comprising:

forming a control gate structure over a substrate;

forming an Oxide-Nitride-Oxide layer over the control gate structure;

depositing a memory gate layer over the Oxide-Nitride-Oxide layer;

forming a first memory gate structure and a second memory gate structure through a first etching process, wherein the first memory gate structure and the second memory gate structure are formed along opposite sidewalls of the control gate structure;

removing the second memory gate structure through a second etching process;

applying a third etching process to a top oxide layer and a silicon nitride layer of the Oxide-Nitride-Oxide layer;

forming a first thin spacer along a sidewall of the first memory gate structure and a second thin spacer along a sidewall of the control gate structure;

applying a fourth etching process to the first memory gate structure;

forming a top spacer over the first memory gate structure; and

forming a first drain/source region adjacent to the first memory gate structure and a second drain/source region adjacent to the control gate structure.

9. The method of claim 8, further comprising:

forming a bottom oxide layer over the substrate and the control gate structure;

forming the silicon nitride layer over the bottom oxide layer; and

forming the top oxide layer over the silicon nitride layer.

10. The method of claim 9, wherein:

the bottom oxide layer is of a thickness of about 50 angstrom;

the silicon nitride layer is of a thickness of about 100 angstrom; and

the top oxide layer is of a thickness of about 100 angstrom.

11. The method of claim 8, further comprising:

forming an opening adjacent to the first memory gate structure;

filling a plurality of conductive materials into the opening to from a conductive region, wherein the conductive region is electrically coupled to the first memory gate structure; and

forming a contact plug over the conductive region, wherein the contact plug is electrically coupled to the conductive region.

12. The method of claim 8, wherein:

the second etching process is an isotropic dry etching process.

13. The method of claim 8, wherein:

the fourth etching process is an isotropic dry etching process.

14. The method of claim 8, wherein:

the silicon nitride layer is a charge storage layer.

15. A method comprising:

forming a control gate structure over a substrate, wherein the control gate structure and the substrate are separated by a gate dielectric layer;

forming a silicon nitride layer over the control gate structure;

depositing a memory gate layer over the silicon nitride layer;

applying a first etching process to the memory gate layer to form a first memory gate structure and a second memory gate structure, wherein the first etching process is applied until a top surface of the first memory gate structure is lower than a top surface of the silicon nitride layer;

applying a second etching process to the silicon nitride layer until the top surface of the silicon nitride layer is lower than the top surface of the first memory gate structure;

forming a first thin spacer layer along the first memory gate structure and a second thin spacer layer along a sidewall of the control gate structure;

applying a third etching process to the first memory gate structure until the top surface of the first memory gate structure is lower than the top surface of the silicon nitride layer; and

forming a memory gate spacer over the first memory gate structure, wherein the memory gate spacer is in direct contact with the first memory gate structure.

16. The method of claim 15, wherein:

the first memory gate structure has a non-planar top surface, and wherein a middle portion of the top surface of the first memory gate structure is lower than an edge portion of the top surface of the first memory gate structure.

17. The method of claim 15, further comprising:

after the step of applying the first etching process to the memory gate layer to form the first memory gate structure and the second memory gate structure and prior to the step of applying the second etching process to the silicon nitride layer, removing the second memory gate structure.

18. The method of claim 15, further comprising:

applying an etching process to the silicon nitride layer to form an L-shaped silicon nitride layer.

19. The method of claim 15, further comprising:

forming a first drain/source region adjacent to the first memory gate structure and a second drain/source region adjacent to the control gate structure.

20. The method of claim 15, further comprising:

depositing a bottom oxide layer over the substrate and the control gate structure;

depositing the silicon nitride layer over the bottom oxide layer; and

depositing a top oxide layer over the silicon nitride layer.