Fabrication of shielded gate trench MOSFET with increased source-metal contact

• US 9,559,179 B2
• Filed: 09/30/2015
• Issued: 01/31/2017
• Est. Priority Date: 08/14/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chen, John
• Primary Examiner(s): Slutsker, Julia
• Application Number:
  US14/871,826
• Publication Number:
  US 20160020291A1
• Time in Patent Office: 489 Days
• Field of Search: 257/330, 257/332
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device formed on a semiconductor substrate having a substrate top surface, comprising: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a gate top dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region; a metal layer disposed over at least a portion of a gate trench opening and at least a portion of the source region, wherein: the source region has a curved sidewall portion that is adjacent to the gate trench, and that extends above the gate top dielectric material.

Claims

1. A semiconductor device formed on a semiconductor substrate having a substrate top surface, comprising:

a gate trench extending from the substrate top surface into the semiconductor substrate;

a gate electrode in the gate trench;

a gate top dielectric material disposed over the gate electrode;

a body region adjacent to the gate trench;

a source region embedded in the body region;

a metal layer disposed over at least a portion of a gate trench opening and at least a portion of the source region, wherein;

the source region has a curved sidewall portion that is adjacent to the gate trench, and that extends above the gate top dielectric material.

2. The semiconductor device of claim 1, wherein the metal layer covers the gate top dielectric material over the gate electrode and contacts at least a portion of a sidewall of the source region facing the gate top dielectric material.

3. The semiconductor device of claim 1, further comprising a shield electrode formed within the gate trench, wherein the gate electrode and the shield electrode are separated by an inter-electrode dielectric material.

4. The semiconductor device of claim 1, wherein the source region has a substantially vertical surface, and at least a portion of the substantially vertical surface is in physical contact with the metal layer.

5. The semiconductor device of claim 1, wherein the gate trench has a trench wall that is at least in part curved.

6. The semiconductor device of claim 5, wherein the curved sidewall portion at least in part conforms to a curved portion of the trench wall.

7. The semiconductor device of claim 1, further comprising a contact trench, and wherein the metal layer is in contact with the source region at at least a portion of a side of the source region facing the contact trench and at least a portion of a side of the source region facing the gate top dielectric material.

8. The semiconductor device of claim 1, wherein top surface of the gate top dielectric material is recessed below top of the source region.

9. The semiconductor device of claim 1, wherein the curved sidewall portion has a convex curvature with respect to the source region.

10. The semiconductor device of claim 1, wherein the metal layer is in contact with the source region on multiple sides.

11. The semiconductor device of claim 1, further comprising a contact trench that is at least in part filled with a conductive plug.

12. The semiconductor device of claim 1, wherein the gate trench includes a portion that is substantially vertical with respect to the substrate top surface.

13. A semiconductor device formed on a semiconductor substrate having a substrate top surface, comprising:

a gate trench extending from the substrate top surface into the semiconductor substrate;

a first electrode disposed in the gate trench;

a second electrode disposed in the gate trench;

a dielectric material disposed in the gate trench, above the first electrode and the second electrode;

a body region adjacent to the gate trench;

a source region embedded in the body region;

a contact trench that allows contact between the source region and the body region; and

a metal layer disposed over at least a portion of a gate trench opening and at least a portion of the source region;

wherein;

the source region extends above a top side of the dielectric material;

the source region has a first side that is substantially aligned with a sidewall of the gate trench, and a second side that is substantially aligned with a sidewall of the contact trench; and

the metal layer is in contact with the source region at at least a portion of the first side and at least a portion of the second side.

14. The semiconductor device of claim 13, wherein:

the source region further has a top side between the first side and the second side; and

the metal layer is further in contact with the source region at at least a portion of the top side.