Structure and method for FinFET device with buried sige oxide

• US 9,559,181 B2
• Filed: 11/26/2013
• Issued: 01/31/2017
• Est. Priority Date: 11/26/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Wang, Chih-Hao, Wu, Zhiqiang, Diaz, Carlos H.
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Jiang, Fang-Xing
• Application Number:
  US14/090,072
• Publication Number:
  US 20150144999A1
• Time in Patent Office: 1,162 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure provides a semiconductor device that includes a substrate of a first semiconductor material; a fin feature having a first portion, a second portion and a third portion stacked on the substrate; an isolation feature formed on the substrate and disposed on sides of the fin feature; semiconductor oxide features including a second semiconductor material, disposed on recessed sidewalls of the second portion, defining dented voids overlying the semiconductor oxide features and underlying the third portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extended into and filling in the dented voids. The first and third portions include the first semiconductor material having a first lattice constant. The second portion includes the second semiconductor material having a second lattice constant different from the first lattice constant.

Claims

1. A semiconductor device comprising:

a substrate of a first semiconductor material having a first lattice constant;

a fin feature formed on the substrate, wherein the fin feature includes a first portion of the first semiconductor material disposed over the substrate;

a second portion of a second semiconductor material disposed over the first portion, wherein the second semiconductor material has a second lattice constant different from the first lattice constant; and

a third portion of the first semiconductor material disposed over the second portion;

an isolation feature formed on the substrate and disposed on sides of the fin feature, wherein the second portion includes recessed sidewalls;

semiconductor oxide features including the second semiconductor material, disposed on the recessed sidewalls of the second portion, defining dented voids overlying the semiconductor oxide features and underlying the third portion of the fin feature, wherein the isolation feature includes an edge portion contacting a sidewall of the semiconductor oxide features, wherein the edge portion of the isolation feature has a top surface below a top surface of the second portion; and

a gate stack disposed on the fin feature and the isolation feature, wherein the gate stack includes a gate dielectric layer extended into and filling in the dented voids, thereby forming side dielectric tips in the dented voids.

2. The semiconductor structure of claim 1, wherein the semiconductor oxide features includes a first dielectric material;

and the side dielectric tips include a second dielectric material different from the first dielectric material.

3. The semiconductor structure of claim 2, wherein the semiconductor oxide features includes at least one of silicon germanium oxide and germanium oxide;

and the side dielectric tips includes a high k dielectric material.

4. The semiconductor structure of claim 3, wherein the high k dielectric material is selected from the group consisting of HfSiO, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfSiO, (Ba,Sr)TiO3 (BST), Al₂O₃, Si3N4, and oxynitrides (SiON).

5. The semiconductor structure of claim 1, wherein the third portion of the fin feature is above a top surface of the isolation feature;

and the side dielectric tips span a vertical dimension H from the top surface of the isolation feature to the bottom surface of the third portion.

6. The semiconductor structure of claim 5, wherein the side dielectric tips span a horizontal dimension W;

the horizontal dimension W ranges between about 1 nm and about 4 nm; and

the vertical dimension H ranges between about 3 nm and about 6 nm.

7. The semiconductor structure of claim 1, further comprising source and drain formed on the fin feature, wherein the source and drain span from each other in the first direction and are interposed by a channel region directly underlying the gate stack.

8. The semiconductor structure of claim 7, wherein the source, the drain, the gate stack and the gate stack are configured as a n-type field effect transistor.

9. The semiconductor structure of claim 1, wherein the first semiconductor material includes silicon and the second semiconductor material include silicon germanium.

10. The semiconductor structure of claim 1, wherein the gate stack further includes a gate electrode disposed on the gate dielectric layer and the gate electrode include metal.

11. The semiconductor structure of claim 7, further comprising a channel region underlying the gate stack, wherein the source, the drain, the gate stack and the gate stack are configured as a n-type field effect transistor.

12. The semiconductor structure of claim 1, wherein the first semiconductor material includes silicon and the second semiconductor material include silicon germanium;

and the gate stack further includes a gate electrode disposed on the gate dielectric layer and the gate electrode include metal.

13. A semiconductor structure, comprising:

an isolation feature formed in a semiconductor substrate;

a fin feature extending in a first direction and formed on the semiconductor substrate and surrounded by the isolation feature, wherein the fin feature includes a first portion extended from the semiconductor substrate;

a second portion of a first semiconductor material disposed on the first portion; and

a third portion of a second semiconductor material disposed on the second portion, wherein the first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant;

a semiconductor oxide feature formed a sidewall of the second portion of the fin feature; and

a gate stack extending in a second direction from over the fin feature to over the isolation feature, wherein the gate stack includes a gate dielectric layer extended to fill in a dented space defined between the semiconductor oxide feature and the third portion of the fin feature, wherein the second direction is perpendicular to the first direction.

14. The semiconductor structure of claim 13, wherein the gate dielectric layer filled in the dented space forms a side dielectric tip on the semiconductor oxide feature;

the semiconductor oxide feature includes a first dielectric material; and

the side dielectric tip includes a second dielectric material different from the first dielectric material.

15. The semiconductor structure of claim 14, wherein the semiconductor oxide features includes at least one of silicon germanium oxide and germanium oxide;

and the side dielectric tip includes a high k dielectric material.

16. The semiconductor structure of claim 15, wherein the high k dielectric material includes HfSiO.

17. The semiconductor structure of claim 13, wherein the third portion of the fin feature is above a top surface of the isolation feature;

the side dielectric tip spans a vertical dimension H from the top surface of the isolation feature to the bottom surface of the third portion ranging between about 3 nm and about 6 nm; and

the side dielectric tip spans a horizontal dimension W ranging between about 1 nm and about 4 nm.

18. The semiconductor structure of claim 13, further comprising source and drain formed on the fin feature, wherein the source and drain span from each other in the first direction and are interposed by a channel region that is defined in the fin feature and is directly underlying the gate stack.

19. A semiconductor device comprising:

a substrate of a first semiconductor material having a first lattice constant;

a fin feature formed on the substrate, wherein the fin feature includes a first portion of the first semiconductor material; and

a second portion of a second semiconductor material and disposed over the first portion, wherein the second semiconductor material has a second lattice constant different from the first lattice constant and wherein the second portion includes recessed sidewalls;

semiconductor oxide features including the second semiconductor material, disposed on the recessed sidewalls of the second portion, defining dented voids overlying the semiconductor oxide features; and

a gate disposed on the fin feature, wherein the gate includes a gate dielectric layer extended into and filling in the dented voids, thereby forming side dielectric tips in the dented voids.

20. The semiconductor structure of claim 19, wherein the semiconductor oxide features include a first dielectric material;

and the side dielectric tips include a second dielectric material different from the first dielectric material.