Devices including gate spacer with gap or void and methods of forming the same

• US 9,559,184 B2
• Filed: 06/15/2015
• Issued: 01/31/2017
• Est. Priority Date: 06/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Liu, Chi-Wen, Leung, Ying-Keung
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US14/739,977
• Publication Number:
  US 20160365426A1
• Time in Patent Office: 596 Days
• Field of Search: 257/288
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Claims

1. A structure comprising:

a substrate with a fin;

a gate stack over the fin;

a contact over the substrate; and

a spacer disposed laterally between the gate stack and the contact, the spacer comprising a first dielectric sidewall portion and a second dielectric sidewall portion, a void being disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

2. The structure of claim 1, wherein the first dielectric sidewall portion and the second dielectric sidewall portion each comprises a low-k dielectric material.

3. The structure of claim 1, wherein the spacer comprises a solid dielectric material fully enclosing the void within the solid dielectric material, the first dielectric sidewall portion and the second dielectric sidewall portion each being a portion of the solid dielectric material.

4. The structure of claim 1, wherein the spacer comprises a first solid dielectric layer and a second solid dielectric layer, each of the first solid dielectric layer and the second solid dielectric layer extending vertically from the substrate, the first solid dielectric layer being the first dielectric sidewall portion, the second solid dielectric layer being the second dielectric sidewall portion, a solid dielectric material being disposed between the first solid dielectric layer and the second solid dielectric layer above the void.

5. The structure of claim 1, wherein the void contacts a surface of the substrate.

6. The structure of claim 1, wherein the spacer laterally encircles the gate stack, and the void laterally encircles the gate stack.

7. The structure of claim 1, wherein the spacer has a first height from a surface of the substrate and in a direction normal to the surface of the substrate, the void having a second height from a bottom surface of the void to a top surface of the void, a ratio of the second height to the first height being in a range from 0.3 to 0.7.

8. The structure of claim 1 further comprising:

a source/drain region in the substrate and proximate to the gate stack, the contact connecting to the source/drain region;

a first inter-layer dielectric layer over the substrate and laterally around the gate stack, the contact being disposed through the first inter-layer dielectric layer; and

a second inter-layer dielectric layer over the first inter-layer dielectric layer, the contact, the gate stack, and the spacer.

9. The structure of claim 8 further comprising:

a first dielectric cap over the contact and the first inter-layer dielectric layer; and

a second dielectric cap over the gate stack, respective top surfaces of the first dielectric cap, the second dielectric cap, and the spacer being co-planar.

10. A structure comprising:

a substrate;

a gate dielectric over the substrate;

a gate electrode over the gate dielectric;

a gate spacer around the gate electrode, the gate spacer comprising a first solid dielectric sidewall portion and a second solid dielectric sidewall portion, a void being between the first solid dielectric sidewall portion and the second solid dielectric sidewall portion, the void being around the gate electrode;

a source/drain region in the substrate and proximate to the gate dielectric and gate electrode; and

a lower contact connecting to the source/drain region, the gate spacer being disposed immediately adjacent to the lower contact and between the lower contact and the gate electrode.

11. The structure of claim 10, wherein the spacer comprises a continuous layer enclosing the void, each of the first solid dielectric sidewall portion and the second solid dielectric sidewall portion being a portion of the continuous layer.

12. The structure of claim 10, wherein the first solid dielectric sidewall portion is a first layer, and the second solid dielectric sidewall portion is a second layer separated from the first layer, the void being disposed between the first layer and the second layer, the void contacting a surface of the substrate, a solid dielectric material being disposed between the first layer and the second layer and above the void.

13. The structure of claim 10 further comprising:

a first inter-layer dielectric layer over the substrate, the gate electrode being in the first inter-layer dielectric layer, the lower contact being through the first inter-layer dielectric layer;

a first dielectric cap over the gate electrode;

a second dielectric cap over the lower contact, top surfaces of the first dielectric cap, the second dielectric cap, and the gate spacer being co-planar;

a second inter-layer dielectric layer over the first dielectric cap, the second dielectric cap, and the gate spacer;

a first upper contact extending through the second inter-layer dielectric layer and the first dielectric cap and connecting to the gate electrode; and

a second upper contact extending through the second inter-layer dielectric layer and the second dielectric cap and connecting to the lower contact.

14. A structure comprising:

a gate dielectric over a substrate;

a gate electrode over the gate dielectric;

a contact in physical connection with the substrate at a point laterally removed from the gate electrode;

a dielectric material surrounding the gate electrode and at least partially located between the gate electrode and the contact, the dielectric material comprising a first material throughout the dielectric material, wherein the dielectric material comprises a first sidewall facing the contact, the first sidewall being straight as the first sidewall extends from a first side of the dielectric material facing the substrate to a second side of the dielectric material opposite the first side; and

a void surrounded by the dielectric material, wherein the void encircles the gate electrode.

15. The structure of claim 14, wherein the dielectric material has a first height and the void has a second height that is between about 0.3 and 0.7 times the first height.

16. The structure of claim 14, wherein the void exposes a portion of the substrate.

17. The structure of claim 14, further comprising an inter-layer dielectric surrounding the contact.

18. The structure of claim 14, further comprising a dielectric cap located over the gate electrode.

19. The structure of claim 18, wherein the dielectric cap has a top surface that is planar with a top surface of the dielectric material.

20. The structure of claim 14, wherein a portion of the dielectric material is interposed between the void and the substrate.