Semiconductor device and method of manufacture therefor

• US 9,559,198 B2
• Filed: 08/27/2013
• Issued: 01/31/2017
• Est. Priority Date: 08/27/2013
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Stefanov, Evgueniy, de Fresart, Edouard, Dupuy, Philippe
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US14/912,346
• Publication Number:
  US 20160197176A1
• Time in Patent Office: 1,253 Days
• Field of Search: 257/334
• US Class Current: 1/1
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device comprises a first contact layer, a first drift layer adjacent the first contact layer, a buried body layer adjacent the first drift layer and a second contact layer. A first vertical trench and a second vertical trench are provided, the first and second vertical trenches being spaced with respect to each other and extending from the second contact layer to substantially beyond the buried body layer. A second drift layer is also provided and sandwiched between the buried body layer and the second contact layer.

Claims

1. A bi-directional trench field effect power transistor, comprising:

a substrate with a substrate top surface;

a layer stack extending over the substrate top surface, a first vertical trench and a second vertical trench being present in the layer stack, each of said first and second vertical trenches extending in a vertical direction from a top layer of the layer stack towards the substrate;

a first current terminal and a second current terminal, the first current terminal being situated in said vertical direction below the second current terminal and the second current terminal being situated on or above the top layer; and

an electrical path which can be selectively enabled or disabled to allow current to flow in a first direction or a second direction, opposite to the first direction, between the first current terminal and the second current terminal, the electrical path comprising;

a body extending laterally between the first and second vertical trenches and vertically between said first current terminal and said second current terminal;

a first drift region extending, in said vertical direction, between the body and the first current terminal;

a second drift region extending, in said vertical direction, between the body and the second current terminal;

wherein the first vertical trench and the second vertical trench have the same of option (a) and/or (b);

option (a) being;

the first and second vertical trenches extend, in said vertical direction, from said top layer beyond an upper boundary of the first drift region, and in a lateral direction parallel to the substrate top-surface electrically isolate, and define, the first drift region;

option (b) being;

each of said first and second vertical trenches comprising;

a gate electrode in an first part of the vertical trench, the gate electrode being electrically coupled to the body, for forming, when a suitable voltage is applied to the gate, a vertical channel in the body through which a current can flow from the first drift region to the second drift region or vice versa;

a lower shield plate, the shield plate being situated in a lower part of the trench, the lower part being closer to the substrate than the first part, for generating an accumulation layer in the first drift region when the lower shield plate is biased with respect to the first current terminal in a first polarity and locally reducing the electrical field density when the lower shield plate is biased with respect to the first current terminal in a second polarity; and

a body-side vertical sidewall, and another vertical sidewall facing the body-side vertical sidewall, of which at least the body-side vertical sidewall is covered with a dielectric which separates the gate electrode and the shield plate from the body-side vertical sidewall, the dielectric being thicker in the first part than in the lower part.

2. A power transistor as claimed in claim 1, wherein the first and second vertical trenches each further comprise an upper shield plate for generating an accumulation layer in the second drift region when the upper shield plate is biased with respect to the second current terminal in the first polarity and reducing at least locally the electrical field density when the upper shield plate is biased with respect to the second current terminal in the second polarity.

3. A power transistor as claimed in claim 1, wherein the lower shield plate has in said vertical direction a tapered shape pointing towards the substrate.

4. A power transistor as claimed in claim 1, wherein the first and second vertical trenches extend from the top layer at least until the substrate top surface.

5. A power transistor as claimed in claim 4, wherein the vertical trenches extend into the substrate and the shield plate terminates above the substrate.

6. A power transistor as claimed in claim 1, having a current maximum of at least 2 A and/or a positive drain-source break down voltage of at least 45 V and a negative drain-source break down voltage of at least 25 V.

7. A power transistor as claimed in claim 1, comprising separate contacts connected to individually control the voltage and/or current of the gate electrode, the first current terminal, the second current terminal, and the body.

8. A power transistor as claimed in claim 7, comprising further separate contacts connected to individually control the voltage of the lower shield plate and the upper shield plate.

9. A power transistor as claimed in claim 7, wherein the voltage of the lower shield plate and/or the upper shield plate is dependent on the voltage of the second current terminal and the lower shield plate and/or the upper shield plate are connected to the second current terminal.

10. A power transistor as claimed in claim 1, comprising an elongated vertical trench enclosure which, in a plane parallel to the substrate top-surface, encloses the electrical path, the first vertical trench and the second vertical trench being part of the elongated vertical trench enclosure.

11. A power transistor as claimed in claim 1, wherein the elongated vertical trench enclosure comprises an elongated enclosing gate electrode which comprises the gate electrodes of the vertical trenches, and an elongated enclosing lower shield plate which comprises the lower shield plates of the vertical trenches, the enclosing gate electrode enclosing the body and the enclosing lower shield plate enclosing the first drift region.

12. A power transistor as claimed in claim 1, wherein the first and second drift region are of a first conductivity type having a first type of majority charge carriers, and the body is of a second conductivity type having a second type of majority charge carriers opposite to the first type.

13. A power transistor as claimed in claim 12, wherein:

the first and second current terminals are of the first conductivity type;

the concentration of majority charge carriers in the first current terminal is higher than in the first drift region; and

the concentration of majority charge carriers in the second current terminal is higher than in the second drift region.

14. A power transistor as claimed in claim 1, wherein the layer stack comprises a bulk layer of a base material of the first conductivity type with a concentration of majority charge carriers equal to a concentration in the first drift region or in the second drift region, the bulk layer being provided with at least one doped layer in which a doping is different than in the base material, the doped layer having the second conductivity type and/or concentration of majority charge carriers higher than the base material.

15. A power transistor as claimed in claim 14, wherein the doped layers comprise one or more of the group consisting of:

a buried layer of the second conductivity type, in which the body is present,

a source layer of the first conductivity type with a concentration of majority charge carriers higher than the base material, in which the source layer the second current terminal is present, the source layer being separated from the buried layer by a drift layer of the base material which the second drift region is present; and

a drain layer of the first conductivity type with a concentration of majority charge carriers higher than the base material, in which the source layer the first current terminal is present, the source layer being separated from the buried layer by a drift layer of the base material in which the first drift region is present.

16. A power transistor as claimed in claim 1, wherein the substrate is of the first conductivity type, and the first current terminal is provided in the substrate.

17. A semiconductor product, comprising:

a plurality of power transistors, each of the power transistors comprising;

a substrate with a substrate top surface;

a layer stack extending over the substrate top surface, a first vertical trench and a second vertical trench being present in the layer stack, each of said first and second vertical trenches extending in a vertical direction from a top layer of the layer stack towards the substrate;

a first current terminal and a second current terminal, the first current terminal being situated in said vertical direction below the second current terminal and the second current terminal being situated on or above the top layer; and

an electrical path which can be selectively enabled or disabled to allow current to flow in a first direction or a second direction, opposite to the first direction, between the first current terminal and the second current terminal, the electrical path comprising;

a body extending laterally between the first and second vertical trenches and vertically between said first current terminal and said second current terminal;

a first drift region extending, in said vertical direction, between the body and the first current terminal;

a second drift region extending, in said vertical direction, between the body and the second current terminal;

wherein the first vertical trench and the second vertical trench have the same of option (a) and/or (b);

option (a) being;

the first and second vertical trenches extend, in said vertical direction, from said top layer beyond an upper boundary of the first drift region, and in a lateral direction parallel to the substrate top-surface electrically isolate, and define, the first drift region;

option (b) being;

each of said first and second vertical trench comprising;

a gate electrode in an first part of the vertical trench, the gate electrode being electrically coupled to the body, for forming, when a suitable voltage is applied to the gate, a vertical channel in the body through which a current can flow from the first drift region to the second drift region or vice versa;

a lower shield plate, the shield plate being situated in a lower part of the trench, the lower part being closer to the substrate than the first part, for generating an accumulation layer in the first drift region when the lower shield plate is biased with respect to the first current terminal in a first polarity and locally reducing the electrical field density when the lower shield plate is biased with respect to the first current terminal in a second polarity; and

a body-side vertical sidewall, and another vertical sidewall facing the body-side vertical sidewall, of which at least the body-side vertical sidewall is covered with a dielectric which separates the gate electrode and the shield plate from the body-side vertical sidewall, the dielectric being thicker in the first part than in the lower part;

a first current electrode connected to the first current terminal of each of said power transistors;

a second current electrode connected to the second current terminal of each of said power transistor; and

a gate feed connected to the gate electrode of each power transistor wherein the first current electrode, second current electrode and gate feed are connectable to an external power supply.

18. A semiconductor product as claimed in claim 17, wherein the second current electrode is further connected to the shield plate of each transistor.

19. A semiconductor product as claimed in claim 17, further comprising a body electrode connectable to an external power supply and connected to the body of each of said power transistors.

20. A method of manufacturing a power transistor comprising:

providing on a substrate a layer stack extending over said substrate, and providing the layer stack with a first vertical trench and a second vertical trench, each of said vertical trenches extending in a vertical direction from a top layer of the stack towards the substrate;

providing a second current terminal on or above the top layer and a first current terminal, in said vertical direction, below the second current terminal; and

providing an electrical path which can be selectively enabled or disabled to allow current to flow between the first current terminal and the second current terminal, providing the electrical path comprising;

providing a body between said first current terminal and said second current terminal, the body extending laterally between the first and second vertical trenches and vertically;

providing a first drift region, in said vertical direction, between the body and the first current terminal; and

providing a second drift region, in said vertical direction, between the body and the second current terminal;

providing each of said first and second vertical trenches with a gate electrode in a first part of the vertical trench, the gate electrode being electrically coupled to the body;

providing a lower shield plate in a lower part of the trench closer to the substrate than the first part; and

providing a body-side vertical sidewall of each of the vertical trenches with a dielectric which separates the gate electrode and the shield plate from the body-side vertical sidewall, the dielectric being thicker in the first part than in the lower part.