Low-power wide-range level shifter

• US 9,559,673 B2
• Filed: 04/01/2015
• Issued: 01/31/2017
• Est. Priority Date: 04/01/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Grubelich, Bjorn Erik
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US14/676,006
• Publication Number:
  US 20160294373A1
• Time in Patent Office: 671 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence

Abstract

A latch-based level-shifter is provided that includes an edge-triggered pulse generator that drives a switch to switch off and isolate a pair of cross-coupled inverters in the level-shifter from ground for a transition period responsive to rising and falling edges in an input signal.

Claims

1. A circuit, comprising:

a latch including a pair of cross-coupled inverters having a virtual ground node, the latch being configured to level-shift a low-voltage-domain input signal from a low voltage domain into a high-voltage-domain output signal for a high voltage domain, wherein the pair of cross-coupled inverters are configured to be powered by a high power supply voltage for the high voltage domain;

a switch coupled between the virtual ground node and ground;

an edge-triggered pulse generator configured to pulse the switch off for a transition period responsive to rising edges in the low-voltage-domain input signal and responsive to falling edges in the low-voltage-domain input signal;

a first NMOS access transistor coupled to an output node of a first one of the cross-coupled inverters; and

a first inverter powered by low power supply voltage domain, the first inverter being configured to invert the low-voltage-domain input signal into a first inverter output signal, and wherein a gate of the first NMOS access transistor is configured to be driven by the first inverter output signal, and wherein the high power supply voltage is greater than the low power supply voltage.

2. The circuit of claim 1, further comprising:

a second NMOS access transistor coupled to an output node of a remaining second one of the cross-coupled inverters.

3. The circuit of claim 2, further comprising:

a second inverter powered by the low power supply voltage for the low power domain, the second inverter being configured to invert the first inverter output signal into a second inverter output signal, and wherein a gate of the second NMOS access transistor is configured to be driven by the second inverter output signal.

4. The circuit of claim 3, further comprising a third inverter having an input node coupled to the output node of the second cross-coupled inverter, and wherein the third inverter is configured to invert a voltage for the output node of the second cross-coupled inverter to produce the high-voltage-domain output signal.

5. The circuit of claim 1, wherein the edge-triggered pulse generator comprises a logic gate and a delay chain of inverters.

6. The circuit of claim 5, wherein the logic gate comprises an XNOR gate.

7. The circuit of claim 6, wherein the delay chain of inverters comprises an odd number of inverters configured to provide a delayed inverted signal to an input of the XNOR gate.

8. The circuit of claim 6, wherein the switch comprises an NMOS switch transistor having a source coupled to ground and a drain coupled to the virtual ground node for the cross-coupled inverters, and wherein the XNOR gate is configured to drive a gate of the NMOS switch transistor.

9. The circuit of claim 1, wherein a first one of the cross-coupled inverters comprises a first PMOS transistor having a source coupled to a high-voltage-domain power supply node and a drain coupled to a first NMOS transistor having a source coupled to the virtual ground node.

10. The circuit of claim 9, wherein a remaining second one of the cross-coupled inverters comprises a second PMOS transistor having a source coupled to the high-voltage-domain power supply node and a drain coupled to a second NMOS transistor having a source coupled to the virtual ground node.

11. A method, comprising:

powering a latch-based level-shifter including a first cross-coupled inverter cross-coupled with a second cross-coupled inverter with a high power supply voltage from a high power domain;

in a first inverter powered by a low power supply voltage for a low power domain, inverting a low-power-domain input signal into an inverted signal, wherein the high power supply voltage is greater than the low power supply voltage;

driving a gate of a first NMOS access transistor with the inverted signal, wherein a drain of the first NMOS access transistor couples to an input of the first cross-coupled inverter and a drain of the first NMOS access transistor couples to ground;

in the latch-based level-shifter, level-shifting a rising edge of the low-power-domain input signal transitioning from ground to the low power supply voltage to transition a high-power-domain output signal from ground to the high power supply voltage;

responsive to the rising edge of the low-voltage domain input signal, isolating the first cross-coupled inverter and the second cross-coupled inverter from ground for a first transition period; and

upon conclusion of the first transition period, re-coupling the pair of cross-coupled inverters to ground.

12. The method of claim 11, further comprising:

in the latch-based level-shifter, level-shifting a falling edge of the low-voltage domain input signal transitioning from the low power supply voltage to ground to transition the high-voltage domain output signal from the high power supply voltage to ground;

responsive to the falling edge of the low-voltage domain input signal, isolating the pair of cross-coupled inverters from ground for a second transition period; and

upon conclusion of the second transition period, re-coupling the pair of cross-coupled inverters to ground.

13. The method of claim 12, wherein a duration of the first transition period equals a duration of the second transition period.

14. The method of claim 11, wherein isolating the pair of cross-coupled inverters comprises switching off a switch transistor coupled between the pair of cross-coupled inverters and ground.

15. The method of claim 14, wherein switching off the switch transistor comprises switching off an NMOS switch transistor.

16. A circuit, comprising:

a latch including a pair of cross-coupled inverters, the latch being configured to level-shift a low-voltage-domain input signal into a high-voltage-domain output signal;

means for isolating the pair of cross-coupled inverters from ground for a transition period responsive to a transition of the low-voltage-domain input signal from ground to a low supply voltage and responsive to a transition of the low-voltage-domain input signal from the low supply voltage to ground and for recoupling the pair of cross-coupled inverters to ground upon termination of each transition period, wherein a first one of the cross-coupled inverters comprises a first PMOS transistor having a source coupled to a high-voltage-domain power supply node configured to supply a high supply voltage that is greater than the low supply voltage, the first PMOS transistor having a drain coupled to a first NMOS transistor having a source coupled to the means for isolating, and wherein a remaining second one of the cross-couped inverters comprises a second PMOS transistor having a source coupled to the high-voltage-domain power supply node and a drain coupled to a second NMOS transistor having a source coupled to means for isolating;

a first NMOS access transistor coupled to an output node of a first one of the cross-coupled inverters, and

a second NMOS access transistor coupled to an output node of a remaining one of the cross-coupled inverters.