Power and data switch

• US 9,559,685 B1
• Filed: 07/13/2015
• Issued: 01/31/2017
• Est. Priority Date: 07/11/2014
• Status: Active Grant

• Current Assignee: Renesas Design Technology Incorporated
• Original Assignee: Silego Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Li, Jay, Chen, Albert, McDonald, John Othniel
• Primary Examiner(s): Wells, Kenneth B
• Application Number:
  US14/798,289
• Time in Patent Office: 568 Days
• Field of Search: 327/434
• US Class Current: 1/1
• CPC Class Codes: H04B 2203/547 via DC power distribution
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04B 3/56 Circuits for coupling, blocking, or by-passing of signals

Abstract

A single integrated circuit that supports both power switching and data switching is disclosed. In some embodiments, the integrated circuit comprises a driver circuit configured to drive a switch of an associated line in a power mode or in a data mode and one or more decoupling capacitor ground switches, wherein each decoupling capacitor ground switch connects an associated decoupling capacitor to ground in the power mode and wherein each decoupling capacitor ground switch leaves an associated decoupling capacitor floating in the data mode.

Claims

1. An integrated circuit, comprising:

a driver circuit configured to drive a switch of an associated line in a power mode or in a data mode; and

one or more decoupling capacitor ground switches, wherein each decoupling capacitor ground switch connects an associated decoupling capacitor to ground in the power mode and wherein each decoupling capacitor ground switch leaves an associated decoupling capacitor floating in the data mode.

2. The integrated circuit of claim 1, wherein the line comprises a power rail in power mode.

3. The integrated circuit of claim 1, wherein the line comprises a high speed data line in data mode.

4. The integrated circuit of claim 1, wherein the line switch comprises a MOSFET (metal-oxide-semiconductor field-effect transistor).

5. The integrated circuit of claim 1, wherein the line switch comprises a power MOSFET (metal-oxide-semiconductor field-effect transistor).

6. The integrated circuit of claim 1, wherein the line switch comprises two MOSFETs (metal-oxide-semiconductor field-effect transistors) configured in series in a back-to-back reverse blocking configuration.

7. The integrated circuit of claim 1, wherein the driver circuit is configured to drive a gate of the switch to a higher voltage in power mode and a lower voltage in data mode.

8. The integrated circuit of claim 1, wherein the driver circuit comprises a charge pump.

9. The integrated circuit of claim 1, wherein the integrated circuit comprises an input control pin for selecting the power mode or data mode.

10. The integrated circuit of claim 1, wherein the integrated circuit comprises a power supply input pin.

11. A method comprising,

configuring a driver circuit to drive a switch of an associated line in a power mode or in a data mode;

and

configuring each of one or more decoupling capacitor ground switches to connect an associated decoupling capacitor to ground in the power mode and to leave an associated decoupling capacitor floating in the data mode.

12. The method of claim 11, wherein the line comprises a power rail in power mode.

13. The method of claim 11, wherein the line comprises a high speed data line in data mode.

14. The method of claim 11, wherein the line switch comprises a MOSFET (metal-oxide-semiconductor field-effect transistor).

15. The method of claim 11, wherein the line switch comprises a power MOSFET (metal-oxide-semiconductor field-effect transistor).

16. The method of claim 11, wherein the line switch comprises two MOSFETs (metal-oxide-semiconductor field-effect transistors) configured in series in a back-to-back reverse blocking configuration.

17. The method of claim 11, wherein the driver circuit is configured to drive a gate of the switch to a higher voltage in power mode and a lower voltage in data mode.

18. The method of claim 11, wherein the driver circuit comprises a charge pump.

19. The method of claim 11, further comprising configuring an input pin of an associated integrated circuit as a control signal for selecting the power mode or data mode.

20. The method of claim 11, further comprising configuring an input pin of an associated integrated circuit as a power supply input pin.