Semiconductor device, power control device and electronic system

• US 9,559,687 B2
• Filed: 08/21/2015
• Issued: 01/31/2017
• Est. Priority Date: 08/25/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kanda, Ryo, Umezu, Kazuyuki, Kurihara, Tomonobu, Nagatsu, Takahiro, Nakahara, Yasushi, Kaya, Yoshinori, Toda, Tetsu, Nakamura, Junichi
• Primary Examiner(s): Paul, Antony M
• Application Number:
  US14/832,867
• Publication Number:
  US 20160056818A1
• Time in Patent Office: 529 Days
• Field of Search: 363/10, 363/40, 363/95, 363/120, 363/53, 363/55, 363/57, 363/60, 363/70, 363/77, 363/109, 363/123, 363/159, 363/174, 363/175, 438/15, 438/26, 318/800, 318/801, 318/400.01, 318/700, 318/727, 318/400.26, 318/400.27, 318/400.28, 318/432
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48096 the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H02P 27/06 using dc to ac converters or inverters H02P27/05 takes precedence
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.

Claims

1. A semiconductor device configured with a single semiconductor chip comprising:

a termination region with a ring-like shape;

a first region provided outside the termination region in which a circuit is formed to operate with a first power supply voltage with a reference voltage as the reference; and

a second region provided inside the termination region in which a circuit is formed to operate with a second power supply voltage with a floating voltage as the reference is formed,

wherein the semiconductor device includes;

a high side driver formed in the second region to drive a high side transistor provided outside the semiconductor device;

a level shift circuit for converting a signal with the reference voltage as the reference into a signal with the floating voltage as the reference, and outputs to the second region;

a first transistor formed in the termination region at a position between a first power supply terminal combined with the first power supply voltage, and a second power supply terminal combined with the second power supply voltage;

a second transistor formed in the termination region at a position between the second power supply terminal and a sense node, and driven by the first power supply voltage; and

a comparator circuit formed in the first region to drive the first transistor to be ON when the voltage of the sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage,

wherein the first transistor charges a capacitor provided outside the semiconductor device at a position between the second power supply terminal and the terminal combined with the floating voltage,

wherein the second transistor is a depression type transistor.

2. A semiconductor device according to claim 1,

wherein each of the first transistor and the second transistor is formed with the circumferential direction of the ring as the gate width,

wherein the gate width of the first transistor is greater than the gate width of the second transistor.

3. A semiconductor device according to claim 2,

wherein the level shift circuit includes a third transistor and a fourth transistor that are formed in the termination region,

wherein the second transistor is formed in a region between the region of the third transistor and the region of the fourth transistor, which is on the side of the shorter distance in the circumferential direction of the ring,

wherein the first transistor is formed in a region between the region of the third transistor and the region of the fourth transistor, which is on the side of the longer distance in the circumferential direction of the ring.

4. A semiconductor device according to claim 1,

wherein the first transistor is a depression type transistor.

5. A power control device configured with a single package comprising:

a reference terminal combined with a reference voltage;

a first power supply terminal combined with a first power supply voltage;

a second power supply terminal combined with a second power supply voltage;

a third power supply terminal combined with a third power supply voltage with a voltage value higher than the first power supply voltage;

a load drive terminal;

a high side transistor provided between the third power supply terminal and the load drive terminal;

a low side transistor provided between the load drive terminal and the reference terminal; and

a semiconductor chip for driving the high side transistor and the low side transistor,

wherein the semiconductor chip includes;

a termination region with a ring-like shape;

a first region provided outside the termination region in which a circuit is formed to operate with a first power supply voltage with the reference voltage as the reference; and

a second region provided inside the termination region in which a circuit is formed to operate with the second power supply voltage with the voltage of the load drive terminal as the reference,

wherein the semiconductor chip includes;

a low side driver formed in the first region to drive the low side transistor;

a level shift circuit for converting a signal generated in the first region with the reference voltage as the reference into a signal with the voltage of the load drive terminal as the reference, and outputting to the second region;

a high side driver formed in the second region to drive the high side transistor;

a first transistor formed in the termination region at a position between the first power supply terminal and the second power supply terminal;

a second transistor formed in the termination region at a position between the second power supply terminal and a sense node, being driven by the first power voltage; and

a comparator circuit formed in the first region to drive the first transistor to be ON when the voltage of the sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage,

wherein the first transistor charges a capacitor provided outside the power control device at a position between the second power supply terminal and the load drive terminal,

wherein the second transistor is a depression type transistor.

6. A power control device according to claim 5,

wherein each of the first transistor and the second transistor is formed with the circumferential direction of the ring in the termination region as the gate width,

wherein the gate width of the first transistor is greater than the gate width of the second transistor.

7. A power control device according to claim 6,

wherein the level shift circuit includes a third transistor and a fourth transistor that are formed in the termination region,

wherein the second transistor is formed in a region between the region of the third transistor and the region of the fourth transistor, which is on the side of the shorter distance in the circumferential direction of the ring,

wherein the first transistor is formed in a region between the region of the third transistor and the region of the fourth transistor, which is on the side of the longer distance in the circumferential direction of the ring.

8. A power control device according to claim 5,

wherein the first transistor is a depression type transistor.

9. A power control device according to claim 5,

wherein the power control device comprises three sets of each of the second power supply terminal, the load drive terminal, the high side transistor, and the low side transistor,

wherein each of the three high side transistors is provided between the third power supply terminal and each of the three load drive terminals,

wherein each of the three low side transistors is provided between each of the three load drive terminals and the reference terminal,

wherein the semiconductor chip is provided with three regions of each of the termination region, the first region, and the second region.

10. A power control device according to claim 9, further comprising:

a wiring substrate on which the semiconductor chip is mounted; and

a bonding wire for combining each of the three high side transistors and each of the three low side transistors.

11. In a power control device according to claim 9,

wherein each of the three high side transistors and each of the three low side transistors is an IGBT.

12. An electronic system comprising:

a reference terminal combined with a reference voltage;

a first power supply terminal combined with a first power supply voltage;

a second power supply terminal combined with a second power supply voltage;

a third power supply terminal combined with a third power supply voltage having a voltage value higher than the first power supply voltage;

a load drive terminal;

a high side transistor provided between the third power supply terminal and the load drive terminal;

a low side transistor provided between the load drive terminal and the reference terminal;

a capacitor provided between the second power supply terminal and the load drive terminal;

a semiconductor chip for driving the high side transistor and the low side transistor; and

a load circuit combined with the load drive terminal,

wherein the semiconductor chip includes;

a termination region with a ring-like shape;

a first region provided outside the termination region, in which a circuit is formed to operate with the first power supply voltage with the reference voltage as the reference; and

a second region provided inside the termination region, in which a circuit is formed to operate with the second power supply voltage with the voltage of the load drive terminal as the reference,

wherein the semiconductor chip includes;

a low side driver formed in the first region to drive the low side transistor;

a level shift circuit for converting a signal generated in the first region with the reference voltage as the reference into a signal with the voltage of the load drive terminal as the reference, and outputting to the second region;

a high side driver formed in the second region to drive the high side transistor;

a first transistor formed in the termination region at a position between the first power supply terminal and the second power supply terminal;

a second transistor formed in the termination region at a position between the second power supply terminal and a sense node, being driven by the first power supply voltage; and

a comparator circuit formed in the first region to drive the first transistor to be ON when the voltage of the sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage,

wherein the second transistor is a depression type transistor.

13. An electronic system according to claim 12,

wherein each of the first transistor and the second transistor is formed with the circumferential direction of the ring in the termination region as the gate width,

wherein the gate width of the first transistor is greater than the gate width of the second transistor.

14. An electronic system according to claim 13,

wherein the level shift circuit includes a third transistor and a fourth transistor that are formed in the termination region,

wherein the second transistor is formed in a region between the region of the third transistor and the region of the fourth transistor, which is on the side of the shorter distance in the circumferential direction of the ring,

wherein the first transistor is formed in a region between the region of the third transistor and the region of the fourth transistor, which is on the side of the longer distance in the circumferential direction of the ring.

15. An electronic system according to claim 12,

wherein the electronic system includes three sets of each of the second power supply terminal, the load drive terminal, the high side transistor, the low side transistor, and the capacitor,

wherein each of the three high side transistors is provided between the third power supply terminal and each of the three load drive terminals,

wherein each of the three low side transistors is provided between each of the three load drive terminals and the reference terminal,

wherein each of the three capacitors is provide between each of the three second power supply terminals and each of the three load drive terminals,

wherein the semiconductor chip is provided with three regions of each of the termination region, the first region, and the second region.

16. An electronic system according to claim 15,

wherein the load circuit is a motor driven by a voltage of 150 V or more.