Real-time analysis of quality of service for multimedia traffic in a local area network

• US 9,559,975 B1
• Filed: 09/29/2012
• Issued: 01/31/2017
• Est. Priority Date: 09/29/2012
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Chen, Paul, Cha, Derek
• Primary Examiner(s): Ebrahim, Anez
• Application Number:
  US13/631,970
• Time in Patent Office: 1,585 Days
• US Class Current: 1/1
• CPC Class Codes: H04L 43/16 Threshold monitoring
• CPC Class Codes: H04L 43/18 Protocol analysers
• CPC Class Codes: H04L 45/302 Route determination based on requested QoS
• CPC Class Codes: H04L 47/11 Identifying congestion
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority

Abstract

The embodiments relate to quality of service (QOS) features for a router, especially a router used in a home network or local area network. In the embodiments, the router is enhanced to be capable of measuring, detecting traffic sessions, and analyzing traffic in real time. The real-time analysis identifies traffic sessions in the data traffic and provides QOS to the traffic sessions. The QOS features are autonomous and do not require user configuration or intervention. In some embodiments, the real-time analysis and QOS features are triggered during periods of congestion.

Claims

1. A router comprising:

an internal communications facility;

a set of network interfaces coupled to the internal communications facility;

a shared memory, coupled to the internal communications facility, providing a set of queues; and

a processor, coupled to the internal communications facility, configured to;

detect a level of congestion on at least one of the network interfaces;

responsive to the congestion level being below a threshold level, route packets through the router according to a first mode; and

responsive to the congestion level being above the threshold level, activate a hardware accelerator and route packets according to a second mode, wherein the hardware accelerator is configured to accelerate placement of packets into the set of queues via an expedited communications path over a bus,

wherein, in the first mode, the processor is configured to;

read header information from the packets; and

route the packets to a next hop based on a route lookup corresponding to the header information, and

wherein, in the second mode, the processor is configured to;

cooperate with the hardware accelerator to detect, in real time, sessions in data traffic based on information from portions of the headers in the packets and a current state of a traffic session, wherein the current state of the traffic session is based on packets previously exchanged downstream or upstream between a source and a destination of the traffic session;

queue packets that are part of detected sessions based on a size of the packets and a desired quality of service for the session; and

forward the queued packets that belong to the traffic sessions in accordance with the desired quality of service.

2. The router of claim 1, wherein the set of network interfaces comprises an Ethernet interface.

3. The router of claim 1, wherein the set of network interfaces comprises a wireless network interface.

4. The router of claim 1, wherein the set of queues comprises a respective subqueue at a top of a queue allocated for packets that are smaller than a threshold size.

5. The router of claim 1, wherein, in the second mode, the processor is further configured to limit best-effort traffic traveling upstream to a wide area network below a threshold bandwidth.

6. The router of claim 1, wherein the hardware accelerator comprises a chipset coupled to the processor to perform instructions within a real-time constraint.

7. The router of claim 6, wherein the hardware accelerator further comprises the expedited communications path for transferring packets to the set of queues.

8. The router of claim 7, wherein the set of queues comprises a special queue reserved for packets designated by the hardware accelerator.

9. A method, comprising:

detecting a level of congestion on at least one network interface;

responsive to the congestion level being below a threshold level;

reading header information from packets received via the at least one network interface; and

routing the packets to a next hop based on a route lookup corresponding to the header information; and

responsive to the congestion level being above the threshold level;

activating a hardware accelerator, wherein the hardware accelerator is configured to accelerate placement of packets into a set of queues via an expedited communications path over a bus;

detecting, in real time, sessions in data traffic based on information from portions of the headers in the packets and a current state of a traffic session, wherein the current state of the traffic session is based on packets previously exchanged downstream or upstream between a source and a destination of the traffic session;

queuing packets that are part of detected sessions based on a size of the packets and a desired quality of service for the session; and

forwarding the queued packets that belong to the traffic sessions in accordance with the desired quality of service.

10. The method of claim 9, wherein the at least one network interface comprises an Ethernet interface.

11. The method of claim 9, wherein the at least one network interface comprises a wireless network interface.

12. The method of claim 9, wherein the set of queues comprises a respective subqueue at a top of a queue allocated for packets that are smaller than a threshold size.

13. The method of claim 9, further comprising:

responsive to the congestion level being above the threshold level, limiting best-effort traffic traveling upstream to a wide area network below a threshold bandwidth.

14. The method of claim 9, wherein the hardware accelerator comprises a chipset coupled to a processor to perform instructions within a real-time constraint.

15. The method of claim 9, wherein the hardware accelerator comprises the expedited communications path for transferring packets to the set of queues.

16. The method of claim 9, wherein the set of queues comprises a special queue reserved for packets designated by the hardware accelerator.

17. A non-transitory computer-readable medium having stored thereon instructions that, when executed by a processor, cause the processor to perform operations comprising:

detecting a level of congestion on at least one network interface;

responsive to the congestion level being below a threshold level;

reading header information from packets received via the at least one network interface; and

routing the packets to a next hop based on a route lookup corresponding to the header information; and

responsive to the congestion level being above the threshold level;

activating a hardware accelerator, wherein the hardware accelerator is configured to accelerate placement of packets into a set of queues via an expedited communications path over a bus;

detecting, in real time, sessions in data traffic based on information from portions of the headers in the packets and a current state of a traffic session, wherein the current state of the traffic session is based on packets previously exchanged downstream or upstream between a source and a destination of the traffic session;

queuing packets that are part of detected sessions based on a size of the packets and a desired quality of service for the session; and

forwarding the queued packets that belong to the traffic sessions in accordance with the desired quality of service.

18. The non-transitory computer-readable medium of claim 17, wherein the operations further comprise:

responsive to the congestion level being above the threshold level, limiting best-effort traffic traveling upstream to a wide area network below a threshold bandwidth.

19. The non-transitory computer-readable medium of claim 17, wherein the hardware accelerator comprises one or more of a chipset coupled to the processor to perform instructions within a real-time constraint or the expedited communications path for transferring packets to the set of queues.

20. The non-transitory computer-readable medium of claim 17, wherein the set of queues comprises a special queue reserved for packets designated by the hardware accelerator.