×

Packet shaping in a network processor

  • US 9,559,982 B2
  • Filed: 02/28/2014
  • Issued: 01/31/2017
  • Est. Priority Date: 02/28/2014
  • Status: Active Grant
First Claim
Patent Images

1. A circuit for managing transmittal of packets, the circuit comprising:

  • a packet descriptor manager (PDM) circuit module configured to generate a metapacket from a command signal, the metapacket indicating a size and a destination of a packet to be transmitted by the circuit, the metapacket including an entry stating the size of the packet;

    a packet scheduling engine (PSE) circuit module configured to compare a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, the PSE determining an order in which to transmit the packet among a plurality of packets based on the comparison; and

    a packet engines and buffering (PEB) circuit module configured to process the packet and cause a processed packet to be transmitted toward the destination according to the order determined by the PSE;

    wherein the PSE is further configured to compare, for a plurality of nodes in a path between the circuit and the destination, a packet transmission rate associated with the node against at least one of a peak rate and a committed rate associated with the node, the PSE determining the order based on the comparisons.

View all claims
  • 6 Assignments
Timeline View
Assignment View
    ×
    ×