Testing apparatus for providing per pin level setting

• US 9,562,947 B2
• Filed: 05/17/2013
• Issued: 02/07/2017
• Est. Priority Date: 03/25/2013
• Status: Active Grant

• Current Assignee: Test Research Incorporated
• Original Assignee: Test Research Incorporated
• Inventors: Chen, Hsin-Hao, Kuo, Po-Shen
• Primary Examiner(s): Phan, Huy Q
• Assistant Examiner(s): RIOS RUSSO, RAUL J
• Application Number:
  US13/897,239
• Publication Number:
  US 20140285228A1
• Time in Patent Office: 1,362 Days
• Field of Search: 324/500, 324/537, 324/554, 324/700, 324/756.01, 324/756.02, 361/93.1
• US Class Current: 1/1
• CPC Class Codes: G01R 1/0466 concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G01R 31/327 Testing of circuit interrupters, switches or circuit-breakers

Abstract

A testing apparatus for providing per pin level setting is disclosed, and the testing apparatus includes a control unit and a filter circuit, where the control unit is electrically connected to the filter circuit. The control unit includes a field programmable gate array (FPGA) for providing a PWM signal. The filter circuit receives the PWM signal and outputs at least one DC voltage.

Claims

1. A testing apparatus for providing per pin level setting, the testing apparatus comprising:

a pin driver and pin receiver having an input, and an output connected to a tested circuit;

a filter circuit connected to the input of the pin driver and pin receiver; and

a control unit comprising;

a field programmable gate array (FPGA) for providing a pulse width modulation (PWM) signal; and

at least one inverter having an input terminal in direct contact with the FPGA for receiving the PWM signal, and an output terminal in direct contact with the filter circuit, so that the filter circuit receives the PWM signal form the output terminal of the at least one inverter and outputs at least one direct current (DC) voltage to the input of the pin driver and pin receiver,

wherein the FPGA of the control unit is connected to the filter circuit via the inverter, and the FPGA of the control unit does not receive any signal fed back from the filter circuit.

2. The testing apparatus of claim 1, wherein the pin driver and pin receiver receives the DC voltage so as to test a tested circuit.

3. The testing apparatus of claim 1, wherein the filter circuit is a low-pass filter for attenuating a high frequency portion of the PWM signal and outputting the DC voltage.

4. The testing apparatus of claim 3, wherein the low-pass filter is a RC low-pass filter.

5. The testing apparatus of claim 4, wherein the RC low-pass filter comprises:

a first resistor, wherein a first terminal of the first resistor is connected to an output terminal of the control unit;

a first capacitor, wherein a first terminal of the first capacitor is connected to a second terminal of the first resistor, and a second terminal of the first capacitor is grounded;

a second resistor, wherein a first terminal of the second resistor is connected to the first terminal of the first capacitor; and

a second capacitor, wherein a first terminal of the second capacitor is connected to a second terminal of the second resistor and a load, and a second terminal of the second capacitor is grounded.