Capacitance detecting method, integrated circuit, touch sensor system, and electronic device
First Claim
1. A capacitance detecting method, comprising the steps of:
- (A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , and where M<
N) each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and
(B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line,the step (A) driving, when the analog integrator is reset, the M drive lines at a first voltage represented by a voltage Vref and driving, when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the M drive lines at (i) a second voltage for an element of +1 in the code sequences, the second voltage being represented by a voltage (Vref+V), and (ii) a third voltage for an element of −
1 in the code sequences, the third voltage being represented by a voltage (Vref−
V).
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Abstract
A capacitance detecting method disclosed herein, which achieves a good detection accuracy, a good resolution, and a high-speed operation, (A) (a) drives, on the basis of code sequences (di (=di1, di2, . . . , diN, where i=1, . . . , M)) which are orthogonal to one another and include ±1 and each of which has a length N, drive lines (DL1 through DLM) in parallel for each of (I) a first capacitance column (Ci1) between the drive lines and a first sense line (SL1) and (II) a second capacitance column (Ci2) between the drive lines and a second sense line (SL2) so that voltages ±V are applied and (b) outputs outputs (sFirst=(s11, s12, . . . , s1N)) from the first capacitance column (Ci1) and outputs (sSecond=(s21, s22, . . . , s2N)) from the second capacitance column (Ci2), and (B) estimates (a) on the basis of a first inner product operation of the outputs (sFirst) and the code sequences (di), a first capacitance value in the first capacitance column (Ci1) and (b) on the basis of a second inner product operation of the outputs (sSecond) and the code sequences (di), a second capacitance value in the second capacitance column (Ci2).
30 Citations
7 Claims
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1. A capacitance detecting method, comprising the steps of:
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(A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , and where M<
N) each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and(B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the step (A) driving, when the analog integrator is reset, the M drive lines at a first voltage represented by a voltage Vref and driving, when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the M drive lines at (i) a second voltage for an element of +1 in the code sequences, the second voltage being represented by a voltage (Vref+V), and (ii) a third voltage for an element of −
1 in the code sequences, the third voltage being represented by a voltage (Vref−
V).
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2. A capacitance detecting method, comprising the steps of:
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(A) (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , and where M<
N) each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; and(B) estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the capacitance detecting method further comprising, before the step (A), the step of; (C) (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at a first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator, (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as first offset outputs and second offset outputs, respectively, and (c) storing the first and second offset outputs in a memory. - View Dependent Claims (3, 4)
the step (B) estimates (a) the first capacitance value on a basis of a third inner product operation of (I) a result obtained by subtracting, from the outputs sFirst, the first offset outputs stored in the memory and (II) the code sequences di and (b) the second capacitance value on a basis of a fourth inner product operation of (I) a result obtained by subtracting, from the outputs sSecond, the second offset outputs stored in the memory and (II) the code sequences di.
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4. The capacitance detecting method according to claim 2,
wherein: the step (C) (I) repeats a plurality of times an operation of (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at the first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator and (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as the first offset outputs and the second offset outputs, respectively, and (II) averages a plurality of sets of the first and second offset outputs read out and then stores in the memory a result of the averaging.
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5. An integrated circuit, comprising:
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a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , and where M<
N) each of which has a length N, M drive lines in parallel for each of (I) a first capacitance column Ci1 (i=1, . . . , M) formed between the M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line, and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; andan estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the drive section, before outputting the outputs sFirst and sSecond from the first and second capacitance columns to the analog integrator, (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at a first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator, (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as first offset outputs and second offset outputs, respective, and (c) storing the first and second offset outputs in a memory.
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6. A touch sensor system, comprising:
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a sensor panel including (I) a first capacitance column Ci1 (i=1, . . . , M) formed between M drive lines and a first sense line and (II) a second capacitance column Ci2 (i=1, . . . , M) formed between the M drive lines and a second sense line; and an integrated circuit for controlling the sensor panel, the integrated circuit including; a drive section for (a) driving, on a basis of code sequences di (=di1, di2, . . . , diN, where i=1, . . . , and where M<
N) each of which has a length N, the M drive lines in parallel for each of (I) the first capacitance column Ci1 (i=1, . . . , M) and (II) the second capacitance column Ci2 (i=1, . . . , M), and thus (b) outputting, to an analog integrator, outputs sFirst=(s11, s12, . . . , s1N) from the first capacitance column and outputs sSecond=(s21, s22, . . . , s2N) from the second capacitance column; andan estimation section for estimating (a) on a basis of a first inner product operation of the outputs sFirst and the code sequences di, a first capacitance value in the first capacitance column which first capacitance value corresponds to a k1-th drive line and (b) on a basis of a second inner product operation of the outputs sSecond and the code sequences di, a second capacitance value in the second capacitance column which second capacitance value corresponds to a k2-th drive line, the drive section, before outputting the outputs sFirst and sSecond from the first and second capacitance columns to the analog integrator, (a) driving, when the analog integrator is reset and when the outputs sFirst and sSecond from the first and second capacitance columns are sampled, the drive lines at a first voltage so that the outputs sFirst and sSecond from the first and second capacitance columns are outputted to the analog integrator, (b) reading out, from the analog integrator, the outputs sFirst and sSecond from the first and second capacitance columns as first offset outputs and second offset outputs, respective, and (c) storing the first and second offset outputs in a memory. - View Dependent Claims (7)
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Specification