Data storage device, user device and data write method

• US 9,563,549 B2
• Filed: 09/22/2011
• Issued: 02/07/2017
• Est. Priority Date: 11/15/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ahn, Kwang Soo, Choi, Hyun Jin
• Primary Examiner(s): Alsip, Michael
• Application Number:
  US13/239,474
• Publication Number:
  US 20120124276A1
• Time in Patent Office: 1,965 Days
• Field of Search: 711/5, 711/103, 711/206
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data includes a defined super sequential block (SSB), and selects an address mapping mode for the write data in accordance with whether or not a SSB is present.

Claims

1. A hybrid address mapping method for a system including a host and a data storage device, the data storage device including a memory controller directly connected to the host, a buffer memory, and a nonvolatile memory (NVM), the address mapping method comprising:

communicating write data having consecutive logical addresses from the host to the memory controller and storing the write data in a buffer memory, wherein all the logical addresses of the write data are consecutive with one another;

using the memory controller, determining whether the write data includes a super sequential block (SSB) and a residual portion in addition to the SSB;

upon determining that the write data includes the SSB and the residual portion, using a block mapping mode to map a first logical address among the logical addresses associated with the SSB to a corresponding first physical address, while also using a page mapping mode to map a second logical address among the logical addresses associated with a residual portion of the write data excluding write data in the SSB to a corresponding second physical address;

writing the SSB of the write data to the NVM using the block mapping mode; and

writing the residual portion of the write data to the NVM using the page mapping mode,

wherein the SSB is written such that pages of the SSB are interleaved in a plurality of memory blocks of the NVM using at least two channels.

2. The address mapping method of claim 1, wherein the plurality of memory blocks are distributed over a plurality of non-volatile memory devices forming the NVM.

3. The address mapping method of claim 2, wherein the writing of a page among the pages of the SSB using one of the at least two channels is started before completion of the writing of a previous page among the pages of the SSB using another of the at least two channels.

4. A hybrid address mapping method for a system including a host and a data storage device the data storage device including a memory controller directly connected to the host, a buffer memory, and a nonvolatile memory (NVM), the address mapping method comprising:

communicating a write command from the host to the memory controller, wherein the write command includes write data having consecutive logical addresses wherein the write command is a single write command including the write data, and all the logical addresses of the write data are consecutive with one another;

storing the write data in the buffer memory;

determining whether the write data includes a super sequential block (SSB) and a residual portion in addition to the SSB as the write data is stored in the buffer memory;

selecting a block mapping mode to map a first logical address among the logical addresses associated with the SSB to a corresponding first physical address;

selecting a page mapping mode to map a second logical address among the logical addresses associated with the residual portion of the write data to a corresponding second physical address;

writing the SSB of the write data to the NVM using the block mapping mode; and

writing the residual portion of the write data to the NVM using the page mapping mode,

wherein the SSB is written such that pages of the SSB are interleaved in a plurality of memory blocks of the NVM using at least two channels.

5. The address mapping method of claim 4, wherein determining whether the write data includes the SSB as the write data is stored in the buffer memory, selecting the block mapping mode, and selecting the page mapping mode are performed by a buffer layer running on the host, the buffer layer being used to control the communication of the write data from the host to the memory controller and the storing of the write data in the buffer memory.

6. The address mapping method of claim 4, wherein the write command further includes an address mapping mode indication defined by the buffer layer and controlling the selecting of the block mapping mode, and the selecting of the page mapping mode.

7. A data storage device comprising:

a buffer memory configured to temporarily store write data having consecutive logical addresses received from a host, wherein all the logical addresses of the write data are consecutive with one another, the write data includes a super sequential block (SSB) and a residual portion in addition to the SSB, and the SSB includes first logical addresses defined by the host and second logical addresses defined by the host;

a non-volatile memory device configured to store the write data; and

a memory controller configured receive the write data from a host, and map the first and second logical addresses to respective and corresponding first and second physical addresses of the non-volatile memory device,

wherein the memory controller is further configured after storing the write data in the buffer memory to use a block mapping mode for mapping the first logical addresses associated with the SSB of the write data to the corresponding first physical addresses, and to select a page mapping mode for mapping the second logical address associated with the residual portion of the write data to the corresponding second physical addresses,

wherein the SSB of the write data is stored in the non-volatile memory using the block mapping mode, and the residual portion of the write data is stored in the non-volatile memory using the page mapping mode, and

wherein the SSB is stored such that pages of the SSB are interleaved in a plurality of memory blocks of the nonvolatile memory using at least two channels.

8. The data storage device of claim 7, wherein the memory controller is further configured to program the write data in a distributed manner across a plurality of memory blocks defined in the non-volatile memory device.

9. A user device, comprising:

a host including a file system that generates write data having consecutive logical address, wherein all the logical addresses of the write data are consecutive with one another, the write data includes a super sequential block (SSB) and a residual portion in addition to the SSB, first logical addresses associated with a super sequential block (SSB) and second logical addresses associated with the residual portion of the write data, and a buffer layer that generates an address mapping mode indication used to program the write data in a non-volatile memory device, wherein generation of the mapping mode indication is a function of controlling the storage of the write data in a buffer memory; and

a data storage device including the non-volatile memory device, the buffer memory that temporarily stores the write data under the control of the buffer layer, and a memory controller configured to receive the write data from the host, select one of a plurality of mapping modes in accordance with the address mapping mode indication, and map the first and second logical addresses to respective and corresponding first and second physical addresses of the non-volatile memory device according to the selected one of the plurality of mapping modes,

wherein the SSB of the write data is stored in the non-volatile memory using a first mapping mode among the plurality of mapping modes, and the residual portion of the write data is stored in the nonvolatile memory using a different second mapping mode among the plurality of mapping modes, and

wherein the SSB is stored such that pages of the SSB are interleaved in a plurality of memory blocks of the non-volatile memory using at least two channels.

10. The user device of claim 9, wherein the first mapping mode is a block mapping mode and the second mapping mode is a page mapping mode.

11. The user device of claim 10, wherein the host maps the first logical address to the corresponding first physical address using the block mapping mode.

12. The user device of claim 9, wherein the storing of a page among the pages of the SSB using one of the at least two channels is started before completion of the storing of a previous page among the pages of the SSB using another of the at least two channels.