Dynamic prioritization of cache access
First Claim
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1. A method comprising:
- determining, via at least one of one or more processors, that a memory access request to a computer memory results in a cache miss;
determining, over a number of clock cycles, a count of additional cache misses that occurred with a period prior to the cache miss;
comparing the count of the additional cache misses to a tolerance value that corresponds to reservation of a given amount of a plurality of cache state machines available for potential cache hits;
determining, via at least one of the one or more processors, an amount of cache resources used to service the additional cache misses that occurred within the period prior to the cache miss based on the comparing the count of the additional cache misses to the tolerance value, and based on one or more of one or more values derived from a count of cache hits within the period prior to the cache miss or a limit of a plurality of cache state machines to be used to concurrently service cache misses; and
servicing the memory access request based, at least in part, on the amount of cache resources used to service the additional cache misses within the period prior to the cache miss, wherein the servicing the memory access request comprises, in response to the comparing, determining to either reject the memory access request or perform a plurality of cache coherence operations in accordance with the cache miss.
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Abstract
Some embodiments of the inventive subject matter are directed to operations that include determining that an access request to a computer memory results in a cache miss. In some examples, the operations further include determining an amount of cache resources used to service additional cache misses that occurred within a period prior to the cache miss. Furthermore, in some examples, the operations further include servicing the access request to the computer memory based, at least in part, on the amount of the cache resources used to service the additional cache misses within the period prior to the cache miss.
16 Citations
17 Claims
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1. A method comprising:
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determining, via at least one of one or more processors, that a memory access request to a computer memory results in a cache miss; determining, over a number of clock cycles, a count of additional cache misses that occurred with a period prior to the cache miss; comparing the count of the additional cache misses to a tolerance value that corresponds to reservation of a given amount of a plurality of cache state machines available for potential cache hits; determining, via at least one of the one or more processors, an amount of cache resources used to service the additional cache misses that occurred within the period prior to the cache miss based on the comparing the count of the additional cache misses to the tolerance value, and based on one or more of one or more values derived from a count of cache hits within the period prior to the cache miss or a limit of a plurality of cache state machines to be used to concurrently service cache misses; and servicing the memory access request based, at least in part, on the amount of cache resources used to service the additional cache misses within the period prior to the cache miss, wherein the servicing the memory access request comprises, in response to the comparing, determining to either reject the memory access request or perform a plurality of cache coherence operations in accordance with the cache miss. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An apparatus comprising:
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one or more processors; and one or more computer-readable storage devices configured to store instructions, which when executed by at least one of the one or more processors, cause the apparatus to determine whether a memory access request results in a cache miss or cache hit, in response to a cache miss for the memory access request, determine a count of additional cache misses that occurred over a number of clock cycles within a period prior to the cache miss, determine a count of cache hits over the number of clock cycles, compute a ratio of the count of cache hits to the count of the additional cache misses, compare the ratio to a threshold value that corresponds to a limit of a plurality of cache state machines to be used to concurrently service cache misses, and service the memory access request based, at least in part, on determination, based on comparison of the ratio to the threshold value, to either reject the memory access request or perform a plurality of cache coherence operations in accordance with the cache miss. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A computer program product for accessing a computer memory, the computer program product comprising:
a computer readable storage medium having computer usable program code embodied therewith, the computer usable program code configured to; determine that a memory access request to the computer memory results in a cache miss; determine an amount of cache resources used to service additional cache misses that occurred within a period prior to the cache miss; service the memory access request based, at least in part, on the amount of cache resources used to service the additional cache misses within the period prior to the cache miss wherein the computer usable program code configured to service the memory access request based, at least in part, on the amount of cache resources used to service the additional cache misses within the period prior to the cache miss comprises computer usable program code configured to determine a count of additional cache misses over a number of clock cycles that occurred during the period prior to the cache miss, determine a count of cache hits over the number of clock cycles, compute a first value by dividing the count of cache hits by the count of the additional cache misses, compute a second value by dividing the count of cache hits divided by a sum of the count of the additional cache misses plus one, compute a third value, wherein the third value comprises a sum of a tolerance factor and the second value, wherein the tolerance factor corresponds to a limit of the amount of cache resources used to service cache misses within the period, compare the first value to the third value, and based on comparison of the first value to the third value, determine to either reject the memory access request or perform a plurality of cache coherence operations in accordance with a cache miss. - View Dependent Claims (14, 15, 16, 17)
Specification