Stress trim and modified ISPP procedures for PCM

• US 9,564,216 B2
• Filed: 04/09/2015
• Issued: 02/07/2017
• Est. Priority Date: 01/30/2015
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Khwa, Win-San, Su, Tzu-Hsiang, Wu, Chao-I, Li, Hsiang-Pang
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US14/682,903
• Publication Number:
  US 20160225446A1
• Time in Patent Office: 670 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/06 Acceleration testing
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50008 of impedance

Abstract

A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to execute program sequences for selected blocks in the plurality of blocks. The program sequences include patterns of program/verify cycles. The circuit includes logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks. The circuit includes logic to change a particular pattern assigned to a particular block in the plurality of blocks. The circuit includes logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks. The controller includes logic to apply a stress sequence to one of the selected blocks, the stress sequence including stress pulses applied to memory cells in the one of the selected blocks.

Claims

1. A memory circuit, comprising:

a plurality of blocks of memory cells;

a controller including logic to execute program sequences for selected blocks in the plurality of blocks, the program sequences including patterns of program/verify cycles to induce changes in resistance of memory cells to target values representing data;

logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks, wherein program/verify cycles in the patterns of program/verify cycles in program sequences verify whether memory cells have resistances matching a verify level resistance; and

logic to apply a stress sequence to a selected block in the selected blocks to induce a change in program current levels required to cause resistance changes in memory cells in the selected block, the stress sequence being different than the program sequences.

2. The memory circuit of claim 1, wherein the logic to assign different patterns includes a table accessible by the controller.

3. The memory circuit of claim 1, including logic to change a particular pattern assigned to a particular block in the plurality of blocks.

4. The memory circuit of claim 1, including logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks.

5. The memory circuit of claim 1, including logic to change the pattern of the program/verify cycles assigned to the selected block after the stress sequence.

6. The memory circuit of claim 4, wherein a program sequence in the program sequences includes a sequence of program pulses in program/verify cycles in the program sequence, the sequence of program pulses having a range from a lowest magnitude to a highest magnitude, and wherein the statistics include:

for each block in the plurality of blocks, a set of selected magnitudes in the range, and numbers indicating proportions of memory cells in the block that have resistance passing a verify threshold when program pulses having respective selected magnitudes in the set are applied to the memory cells.

7. The memory circuit of claim 6, wherein each program/verify cycle in the pattern of program/verify cycles in the program sequence includes a first verify that verifies whether memory cells in a selected block in the selected blocks have resistance matching the target resistance, comprising:

logic to apply in particular program/verify cycles in the pattern for the selected block that have a program magnitude matching a selected magnitude in the set of selected magnitudes, a second verify to memory cells in the selected block, in addition to the first verify;

logic to compare resistance of the memory cells in the selected block in a comparison against the verify threshold using the second verify; and

logic to update the numbers with results of said comparison for the selected block.

8. A memory circuit, comprising:

a plurality of blocks of programmable resistance memory cells;

a controller including logic to execute program sequences for selected blocks in the plurality of blocks, the program sequences to induce changes in resistance of memory cells in the blocks to target values representing data, the program sequences including patterns of program/verify cycles; and

logic to apply a stress sequence to induce a change in program current levels required to cause resistance changes in memory cells in one of the selected blocks, the stress sequence being different than the program sequences and including stress pulses applied to memory cells in the one of the selected blocks.

9. The memory circuit of claim 8, including logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks;

and logic to cause applying the stress sequence in response to the statistics.

10. The memory circuit of claim 8, including logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks, and circuitry to provide the statistics to the controller, and logic to respond to an external command to cause applying the stress sequence.

11. The memory circuit of claim 8, wherein the program sequences comprise an incremental stepped pulse programming sequence.

12. The memory circuit of claim 8, including logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks, wherein a program sequence in the program sequences includes a sequence of program pulses in program/verify cycles in the program sequence, the sequence of program pulses having a range from a lowest magnitude to a highest magnitude, the statistics include, for each block in the plurality of blocks, a set of selected magnitudes in the range, and numbers indicating proportions of memory cells in the block that have resistance passing a verify threshold when program pulses having respective selected magnitudes in the set are applied to the memory cells, comprising:

for each block in the plurality of blocks, logic to determine a threshold magnitude from the set of selected magnitudes, wherein a first proportion of memory cells in the block that have resistance passing a verify threshold when program pulses having the threshold magnitude are applied to the memory cells is greater than a second proportion of memory cells that have resistance not passing the verify threshold when program pulses having the threshold magnitude are applied to the memory cells.

13. The memory circuit of claim 8, including:

logic to verify whether memory cells in the selected block pass a verify threshold when program pulses having a threshold magnitude are applied to the memory cells;

logic to maintain a logical mask indicating results of executing said logic to verify; and

logic to apply said stress pulses to memory cells in the selected block that have resistance not passing the verify threshold as indicated by the logical mask.

14. The memory circuit of claim 8, wherein a program sequence in the program sequences includes a sequence of program pulses in program/verify cycles in the program sequence, the sequence of program pulses having a range from a lowest magnitude to a highest magnitude, wherein the stress sequence is applied to memory cells in the selected block that have resistance not passing a verify threshold when program pulses having a threshold magnitude are applied to the memory cells, the controller including logic to change a particular pattern assigned to a particular block in the plurality of blocks including:

increasing the lowest magnitude of the range, the increased lowest magnitude being lower than or equal to the threshold magnitude.

15. The memory circuit of claim 8, including logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks, wherein a program sequence in the program sequences includes a sequence of program pulses in program/verify cycles in the program sequence, the sequence of program pulses having a range from a lowest magnitude to a highest magnitude, and wherein the statistics include, for each block in the plurality of blocks, a set of selected magnitudes in the range, and numbers indicating proportions of memory cells in the block that have resistance passing a verify threshold when program pulses having respective selected magnitudes in the set are applied to the memory cells, the controller including logic to change a particular pattern assigned to a particular block in the plurality of blocks including:

removing a selected magnitude having a lowest value from the set; and

adding a new selected magnitude having a value higher than a highest selected magnitude to the set.

16. The memory circuit of claim 8, the controller including logic to respond to an external command to cause stopping the stress sequence.

17. A method for operating a memory circuit comprising a plurality of blocks of memory cells, comprising:

executing program sequences for blocks in the plurality of blocks, the program sequences including patterns of program/verify cycles to induce changes in resistance of memory cells to target values representing data;

assigning different patterns of program/verify cycles to different blocks in the plurality of blocks, wherein program/verify cycles in the patterns of program/verify cycles in program sequences verify whether memory cells have resistances matching a target resistance; and

applying a stress sequence to a selected block in the plurality of blocks to induce a change in program current levels required to cause resistance changes in memory cells in the selected block, the stress sequence being different than the program sequences.

18. The method of claim 17, comprising:

changing a particular pattern assigned to a particular block in the plurality of blocks.

19. The method of claim 17, comprising:

maintaining statistics for blocks in the plurality of blocks, about whether cells in the block pass verify in particular program/verify cycles in the patterns of program/verify cycles assigned to the blocks.

20. The method of claim 17, comprising:

changing the pattern of the program/verify cycles assigned to the selected block after the stress sequence.

21. The method of claim 19, wherein a program sequence in the program sequences includes a sequence of program pulses in program/verify cycles in the program sequence, the sequence of program pulses having a range from a lowest magnitude to a highest magnitude, and wherein the statistics include:

for each block in the plurality of blocks, a set of selected magnitudes in the range, and numbers indicating proportions of memory cells in the block that have resistance passing a verify threshold when program pulses having respective selected magnitudes in the set are applied to the memory cells.

22. The method of claim 21, wherein each program/verify cycle in the program/verify cycles in the program sequence includes a first verify that verifies whether memory cells in a selected block in the selected blocks have resistance matching a target resistance representing a logic value, comprising:

applying, to the memory cells in the selected block, a second verify in addition to the first verify in particular program/verify cycles in the program sequence that have a program magnitude matching a selected magnitude in the set of selected magnitudes;

comparing resistance of the memory cells in the selected block against the verify threshold using the second verify; and

updating the numbers with results of said comparing for the selected block.

23. A method for operating a memory circuit comprising a plurality of blocks of memory cells, comprising:

executing program sequences for selected blocks in the plurality of blocks, the program sequences including patterns of program/verify cycles;

maintaining statistics for blocks in the plurality of blocks, about whether cells in the blocks pass verify in particular program/verify cycles in the patterns of program/verify cycles assigned to the blocks; and

applying a stress sequence to induce a change in program current levels required to cause resistance changes in memory cells in one of the selected blocks, the stress sequence being different than the program sequences and including stress pulses applied to memory cells in the one of the selected blocks.

24. The method of claim 23, including causing said applying the stress sequence in response to the statistics.

25. The method of claim 23, including providing the statistics to a controller, and responding to an external command to cause said applying the stress sequence.

26. The method of claim 23, wherein the program sequences comprise an incremental stepped pulse programming sequence.

27. The method of claim 23, wherein a program sequence in the program sequences includes a sequence of program pulses in program/verify cycles in the program sequence, the sequence of program pulses having a range from a lowest magnitude to a highest magnitude, the statistics include, for each block in the plurality of blocks, a set of selected magnitudes in the range, and numbers indicating proportions of memory cells in the block that have resistance passing a verify threshold when program pulses having respective selected magnitudes in the set are applied to the memory cells, comprising:

for each block in the plurality of blocks, determining a threshold magnitude from the set of selected magnitudes, wherein a first proportion of memory cells in the block that have resistance passing a verify threshold when program pulses having the threshold magnitude are applied to the memory cells is greater than a second proportion of memory cells that have resistance not passing the verify threshold when program pulses having the threshold magnitude are applied to the memory cells.

28. The method of claim 23, including:

verifying whether memory cells in the selected block pass a verify threshold when program pulses having a threshold magnitude are applied to the memory cells;

maintaining a logical mask indicating results of executing said verifying; and

applying stress pulses to memory cells in the selected block that have resistance not passing the verify threshold as indicated by the logical mask.

29. The method of claim 23, wherein a program sequence in the program sequences includes a sequence of program pulses in program/verify cycles in the program sequence, the sequence of program pulses having a range from a lowest magnitude to a highest magnitude, and wherein the stress sequence is applied to memory cells in the selected block that have resistance not passing a verify threshold when program pulses having a threshold magnitude are applied to the memory cells, comprising changing a particular pattern assigned to a particular block in the plurality of blocks including:

increasing the lowest magnitude of the range, the increased lowest magnitude being lower than or equal to the threshold magnitude.

30. The method of claim 23, wherein a program/verify sequence includes a sequence of program pulses in program/verify cycles in the patterns of program/verify cycles, the sequence of program pulses having a range from a lowest magnitude to a highest magnitude, wherein the statistics include, for each block in the plurality of blocks, a set of selected magnitudes in the range, and numbers indicating proportions of memory cells in the block that have resistance passing a verify threshold when program pulses having respective selected magnitudes in the set are applied to the memory cells, comprising changing a particular pattern assigned to a particular block in the plurality of blocks including:

removing a selected magnitude having a lowest value from the set; and

adding a new selected magnitude having a value higher than a highest selected magnitude to the set.

31. The method of claim 23, including responding to an external command to cause stopping the stress sequence.