Non-volatile memory device having vertical structure and method of operating the same

• US 9,564,221 B2
• Filed: 04/08/2016
• Issued: 02/07/2017
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Jae-hun, Kim, Han-soo, Cho, Won-seok, Jang, Jae-hoon, Shim, Sun-il
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US15/094,184
• Publication Number:
  US 20160225451A1
• Time in Patent Office: 305 Days
• Field of Search: 365/185.17
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Claims

1. A non-volatile memory device comprising:

a substrate;

a plurality of semiconductor poles formed on the substrate to extend vertically with respect to the substrate;

a NAND string having a plurality of memory cells stacked on the substrate along a sidewall of one of the plurality of semiconductor poles, the plurality of memory cells arranged in series, and at least one pair of first selection transistors at a first end of the NAND string adjacent to the plurality of memory cells;

a plurality of word lines coupled to the plurality of memory cells of the NAND string; and

a first selection line commonly coupled to the at least one pair of first selection transistors of the NAND string,

wherein the plurality of memory cells comprise control gate electrodes on the sidewall of the one of the semiconductor poles, and the at least one pair of first selection transistors comprises first gate electrodes on the sidewall of the one of the semiconductor poles,

wherein a gate length of each of the control gate electrodes and a gate length of each of the first gate electrodes are substantially equal.

2. The non-volatile memory device of claim 1, further comprising:

a bit line connected to the first end of the NAND string; and

a common source line connected to a second end of the NAND string and opposite to the bit line.

3. The non-volatile memory device of claim 2, wherein the at least one pair of first selection transistors is arranged between the bit line and the plurality of memory cells.

4. The non-volatile memory device of claim 2, wherein the at least one pair of first selection transistors is arranged between the common source line and the plurality of memory cells.

5. The non-volatile memory device of claim 1, wherein the NAND string further comprises at least one pair of second selection transistors at a second end of the NAND string and opposite to the at least one pair of first selection transistors.

6. The non-volatile memory device of claim 5, further comprising a second selection line commonly connected to the at least one pair of second selection transistors of the NAND string.

7. The non-volatile memory device of claim 1, wherein the NAND string further comprises at least one pair of second selection transistors adjacent to the plurality of memory cells and opposite to the at least one pair of first selection transistors.

8. The non-volatile memory device of claim 7, further comprising a second selection line commonly coupled to the at least one pair of second selection transistors of the NAND string.

9. A non-volatile memory device comprising:

a substrate;

a plurality of semiconductor poles formed on the substrate to extend vertically with respect to the substrate;

a NAND string having a plurality of memory cells stacked on the substrate along a sidewall of one of the plurality of semiconductor poles, the NAND string comprising a plurality of control gate electrodes arranged along the sidewall of the one of the plurality of semiconductor poles and at least one set of at least two selection gate electrodes arranged along the sidewall of the one of the semiconductor poles at at least one of two ends of the NAND string adjacent to the plurality of control gate electrodes, wherein the at least one set of at least two selection gate electrodes comprises a first selection gate electrode and a second selection gate electrode;

a selection line; and

at least two contact plugs, the at least two contact plugs having a first contact plug connected between the selection line and the first selection gate electrode and a second contact plug connected between the selection line and the second selection gate electrode,

wherein a gate length of each of the plurality of control gate electrodes and a gate length of each of the at least two selection gate electrodes are substantially equal.

10. The non-volatile memory device of claim 9, wherein the at least one set of at least two selection gate electrodes is arranged farther than the plurality of control gate electrodes with respect to the substrate.

11. The non-volatile memory device of claim 9, wherein heights of the first contact plug and the second contact plug are different from each other.

12. The non-volatile memory device of claim 9, wherein the NAND string further comprises a plurality of storage media, wherein each of the plurality of storage media is interposed between the sidewall at least one of the plurality of semiconductor poles and each of the plurality of control gate electrodes, respectively, and

wherein each of the plurality of storage media comprises a tunneling insulating layer, a charge storing layer and a blocking insulating layer.

13. The non-volatile memory device of claim 9, wherein the NAND string further comprises a plurality of storage media, wherein each of the plurality of storage media is interposed between the sidewall at least one of the plurality of semiconductor poles and each of the plurality of control gate electrodes and between the sidewall of the semiconductor pole and each of the at least two selection gate electrodes, respectively, and

wherein each of the plurality of storage media comprises a tunneling insulating layer, a charge storing layer and a blocking insulating layer.

14. A non-volatile memory device comprising:

a substrate;

a plurality of semiconductor poles formed on the substrate to extend vertically with respect to the substrate;

a NAND string having a plurality of memory cells stacked on the substrate along a sidewall of one of the plurality of semiconductor poles, the NAND string comprising a plurality of control gate electrodes arranged along the sidewall of the one of the plurality of semiconductor poles and at least one set of at least two selection gate electrodes arranged along the sidewall of the one of the semiconductor poles over the plurality of control gate electrodes relative to the substrate;

at least two contact plugs extending vertically with respect to the substrate; and

at least two selection lines farther than the NAND string with respect to the substrate, wherein each of the at least two selection lines is connected to each of the at least two selection gate electrodes via each of the at least two contact plugs, respectively, wherein the at least two contact plugs have different heights, and

wherein a gate length of each of the plurality of control gate electrodes and a gate length of each of the at least two selection gate electrodes are substantially equal.

15. The non-volatile memory device of claim 14, further comprising:

a bit line connected to a first end of the NAND string; and

a common source line connected to a second end of the NAND string.

16. The non-volatile memory device of claim 15, wherein the at least one set of at least two selection gate electrodes is arranged between the bit line and the plurality of control gate electrodes.

17. The non-volatile memory device of claim 16, wherein the at least one set of at least two selection gate electrodes is arranged between the common source line and the plurality of control gate electrodes.

18. The non-volatile memory device of claim 14, further comprising a plurality of word lines farther than the NAND string with respect to the substrate and a plurality of control contact plugs extending vertically with respect to the substrate,

wherein each of the plurality of control gate electrodes is connected to each of the plurality of word lines via each of the plurality of control contact plugs, respectively.

19. The non-volatile memory device of claim 18, wherein the plurality of control contact plugs have different heights.