Methods of forming different FinFET devices with different threshold voltages and integrated circuit products containing such devices

• US 9,564,367 B2
• Filed: 09/13/2012
• Issued: 02/07/2017
• Est. Priority Date: 09/13/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Jacob, Ajey P., Maszara, Witold P., Akarvardar, Kerem
• Primary Examiner(s): Feeney, Brett
• Assistant Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US13/613,508
• Publication Number:
  US 20140070322A1
• Time in Patent Office: 1,608 Days
• Field of Search: 257/314, 257/369, 257/401, 257/347, 257/327, 438/157, 438/199
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.

Claims

1. A method of forming first and second FinFET devices in and above a semiconducting substrate, comprising:

forming a first patterned mask layer above said substrate that exposes a first region of said substrate where said first FinFET device will be formed and masks a second region of said substrate where said second FinFET device will be formed;

with said first patterned mask layer in position, forming a first fin for said first FinFET device, wherein said first fin is comprised of a first semiconductor material that is different from the material of said semiconducting substrate;

removing said first patterned masking layer;

after removing said first patterned masking layer, forming a second patterned masking layer that masks said first region of said substrate and exposes said second region of said substrate where said second FinFET device will be formed; and

after forming said first fin, and with said second patterned masking layer in position, forming a second fin for said second FinFET device, wherein said second fin is comprised of a second semiconductor material that is (a) in contact with said material of said semiconducting substrate, (b) different from the material of said semiconducting substrate and (c) different from said first semiconductor material.

2. The method of claim 1, wherein forming said first fin comprises forming said first fin from one of a Si_1-xGe_x material (where “

x”

ranges from 0-1), a III-V compound semiconductor material, a II-VI compound semiconductor material, or silicon-carbon or combinations thereof.

3. The method of claim 2, wherein forming said second fin comprises forming said second fin from one of a Si_1-xGe_x material (where “

x”

ranges from 0-1), a III-V compound semiconductor material, a II-VI compound semiconductor material, or silicon-carbon or combinations thereof.

4. The method of claim 3, wherein said semiconducting substrate is comprised of silicon.

5. The method of claim 1, wherein forming said first fin comprises performing a first epitaxial deposition process to form said first semiconductor material.

6. The method of claim 5, wherein forming said second fin comprises performing a second epitaxial deposition process to form said second semiconductor material.

13. The method of claim 1 wherein one or more of said first FinFET device and said second FinFET device comprise a plurality of fins.

7. A method of forming first and second FinFET devices in and above a semiconducting substrate, comprising:

forming a first patterned mask layer above said substrate, said first patterned mask layer exposing a first region of said substrate where said first FinFET device will be formed;

with said first patterned mask layer in position, performing at least one process operation through said first patterned mask layer to form a first fin for said first FinFET device, wherein said first fin is comprised of a first semiconductor material that is in contact with and different from the material of said semiconducting substrate;

after forming said first fin, removing said first patterned mask layer;

forming a second patterned mask layer above said substrate, said second patterned mask layer covering said first region of said substrate and exposing a second region of said substrate where said second FinFET device will be formed; and

with said second patterned mask layer in position, performing at least one process operation through said second patterned mask layer to form a second fin for said second FinFET device, wherein said second fin is comprised of a second semiconductor material that is (a) in contact with and different from the material of said semiconducting substrate and (b) different from the material of said first semiconductor material.

8. The method of claim 7, wherein performing said at least one process operation through said first patterned mask layer to form said first fin comprises performing said at least one process operation through said first patterned mask layer to form said first fin from one of a Si_1-xGe_x material (where “

x”

ranges from 0-1), a III-V compound semiconductor material, a II-VI compound semiconductor material, or silicon-carbon or combinations thereof.

9. The method of claim 8, wherein performing said at least one process operation through said second patterned mask layer to form said second fin comprises performing said at least one process operation through said second patterned mask layer to form said second fin from one of a Si_1-xGe_x material (where “

x”

ranges from 0-1), a III-V compound semiconductor material, a II-VI compound semiconductor material, or silicon-carbon or combinations thereof.

10. The method of claim 9, wherein said semiconducting substrate is comprised of silicon.

11. The method of claim 7, wherein performing said at least one process operation through said first patterned mask layer to form said first fin comprises performing a first epitaxial deposition process to form said first semiconductor material.

12. The method of claim 11, wherein performing said at least one process operation through said second patterned mask layer to form said second fin comprises performing a second epitaxial deposition process to form said second semiconductor material.

14. The method of claim 7 wherein one or more of said first FinFET device and said second FinFET device comprise a plurality of fins.