Methods of forming stacked microelectronic dice embedded in a microelectronic substrate

• US 9,564,400 B2
• Filed: 01/28/2016
• Issued: 02/07/2017
• Est. Priority Date: 09/24/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mahnkopf, Reinhard, Molzer, Wolfgang, Memmler, Bernd, Goetz, Edmund, Barth, Hans-Joachim, Albers, Sven, Meyer, Thorsten
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US15/009,731
• Publication Number:
  US 20160148920A1
• Time in Patent Office: 376 Days
• Field of Search: 438/108
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/16148 the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

Claims

1. A method of forming a microelectronic device, comprising:

attaching at least one first microelectronic die to a second microelectronic die with a plurality of interconnects;

disposing an underfill material between the at least one first microelectronic die and the second microelectronic die after attachment;

positioning a first laminate layer proximate the at least one first microelectronic die;

positioning a second laminate layer proximate the second microelectronic die; and

bringing pressure to bear on the first laminate layer and the second laminate layer to form a microelectronic substrate embedding the at least one first microelectronic die and the second microelectronic die therein.

2. The method of claim 1, wherein disposing an underfill material between the at least one first microelectronic die and the second microelectronic die after attachment comprises disposing an underfill material between the at least one first microelectronic die and the second microelectronic die after attachment by capillary action.

3. The method of claim 1, wherein attaching at least one first microelectronic die to a second microelectronic die with a plurality of interconnects comprises attaching an active surface at least one of the first microelectronic die and the second microelectronic die to the other of the first microelectronic die and the second microelectronic die with the plurality of interconnects.

4. The method of claim 1, wherein attaching at least one first microelectronic die to a second microelectronic die with a plurality of interconnects comprises attaching at least one through silicon via at a back surface of at least one of the first microelectronic die and the second microelectronic die to the other of the first microelectronic die and the second microelectronic die with the plurality of interconnects.

5. The method of claim 1, wherein bringing pressure to bear on the first laminate layer and the second laminate layer to form the microelectronic substrate comprises bringing pressure to bear on the first laminate layer and the second laminate layer to form the microelectronic substrate having a first surface proximate the at least one first microelectronic die and a second surface proximate the second microelectronic die.

6. The method of claim 5, further comprising forming an interconnect layer on at least one of the microelectronic substrate first surface and the microelectronic substrate second surface.

7. The method of claim 6, further comprising forming an external interconnect on the interconnect layer.

8. The method of claim 1, further comprising forming at least one conductive via within the microelectronic substrate.

16. The method of claim 1, wherein a portion of the first laminate layer contacts the second laminate layer forming an interface layer.

17. The method of claim 16, wherein the interface abuts one of the underfill material, the first microelectronic die, and the second microelectronic die.

9. A method of forming a microelectronic device, comprising:

disposing an underfill material on at least one of a first microelectronic die and a second microelectronic die;

attaching the at least one first microelectronic die to the second microelectronic die with a plurality of interconnects extending though the underfill material;

positioning a first laminate layer proximate the at least one first microelectronic die;

positioning a second laminate layer proximate the second microelectronic die; and

bringing pressure to bear on the first laminate layer and the second laminate layer to form a microelectronic substrate embedding the at least one first microelectronic die and the second microelectronic die therein.

10. The method of claim 9, wherein attaching at least one first microelectronic die to a second microelectronic die with a plurality of interconnects comprises attaching an active surface at least one of the first microelectronic die and the second microelectronic die to the other of the first microelectronic die and the second microelectronic die with the plurality of interconnects.

11. The method of claim 9, wherein attaching at least one first microelectronic die to a second microelectronic die with a plurality of interconnects comprises attaching at least one through silicon via at a back surface of at least one of the first microelectronic die and the second microelectronic die to the other of the first microelectronic die and the second microelectronic die with the plurality of interconnects.

12. The method of claim 9, wherein bringing pressure to bear on the first laminate layer and the second laminate layer to form the microelectronic substrate comprises bringing pressure to bear on the first laminate layer and the second laminate layer to form the microelectronic substrate having a first surface proximate the at least one first microelectronic die and a second surface proximate the second microelectronic die.

13. The method of claim 12, further comprising forming an interconnect layer on at least one of the microelectronic substrate first surface and the microelectronic substrate second surface.

14. The method of claim 13, further comprising forming an external interconnect on the interconnect layer.

15. The method of claim 9, further comprising forming at least one conductive via within the microelectronic substrate.

18. The method of claim 9, wherein a portion of the first laminate layer contacts the second laminate layer forming an interface layer.

19. The method of claim 18, wherein the interface abuts one of the underfill material, the first microelectronic die, and the second microelectronic die.