Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device

• US 9,564,435 B2
• Filed: 06/29/2015
• Issued: 02/07/2017
• Est. Priority Date: 10/13/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Chung, Eun-ae, Choi, Jung-dal, Nakanishi, Toshiro, Kim, Yu-bin, Nam, Gab-jin, Lee, Dong-kyu, Jiao, Guangfan
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US14/754,400
• Publication Number:
  US 20160104705A1
• Time in Patent Office: 589 Days
• Field of Search: 257/347, 257/E29.264, 257/E29.275
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

Claims

1. A semiconductor device comprising:

a substrate;

a first fin field-effect transistor (FinFET) having a triple-gate structure that is on the substrate; and

a second FinFET having a double-gate structure that is on the substrate,

wherein the first FinFET is disposed in a first region of the substrate comprising logic transistors, and the second FinFET is disposed in a second region of the substrate comprising input/output (I/O) transistors.

2. The semiconductor device of claim 1, further comprising a third FinFET having a double-gate structure that is disposed in the first region of the substrate comprising the logic transistors.

3. The semiconductor device of claim 1, wherein a first fin of the first FinFET has a first height from the substrate, extends in a first direction, and, has a first width in a second direction that is perpendicular to the first direction, and

a second fin of the second FinFET has a second height from the substrate, extends in the first direction, and has a second width in the second direction,

wherein the second height is less than or equal to the first height.

4. The semiconductor device of claim 3, wherein the second width is greater than or equal to the first width.

5. The semiconductor device of claim 3, wherein:

the first FinFET comprises at least one first gate electrode that surrounds a channel region of the first fin, and the first FinFET has a first gate length corresponding to a width of the at least one first gate electrode in the first direction; and

the second FinFET comprises at least one second gate electrode that surrounds a channel region of the second fin, and the second FinFET has a second gate length corresponding to a width of the at least one second gate electrode in the first direction,

wherein the first gate length is less than or equal to the second gate length.

6. The semiconductor device of claim 3, wherein a cross-section of the second fin, perpendicular to the first direction, has a rectangular shape.

7. The semiconductor device of claim 3, wherein a cross-section of the second fin, perpendicular to the first direction, has a trapezoidal shape in which a lower side is longer than an upper side.

8. The semiconductor device of claim 3, wherein in the first FinFET, a channel is to be formed on opposing side surfaces and a top surface of the first fin, and in the second FinFET, a channel is to be formed on opposing side surfaces of the second fin but not on a top surface thereof.

9. The semiconductor device of claim 8, wherein the second FinFET comprises a gate electrode on the opposing side surfaces and the top surface of the second fin,

wherein a dielectric film is disposed between the gate electrode and the second fin, and the dielectric film on the top surface of the second fin is thicker than the dielectric film on the opposing side surfaces of the second fin.

10. The semiconductor device of claim 9, wherein the dielectric film on the top surface of the second fin comprises a capping insulating film on the top surface of the second fin and an outer dielectric film that extends from the dielectric film on the opposing side surfaces of the second fin and covers the capping insulating film.

11. The semiconductor device of claim 8, wherein the second FinFET comprises a gate electrode on the opposing side surfaces of the second fin and a capping insulating film on a top surface of the second fin.

12. The semiconductor device of claim 1, wherein the substrate comprises one selected from the group consisting of silicon (Si), germanium (Ge), a group IV-IV compound semiconductor, and a group III-V compound semiconductor.

13. The semiconductor device of claim 1, wherein the substrate is a silicon bulk substrate or a silicon-on-insulator (SOI) substrate.

14. A semiconductor device comprising:

a substrate;

a first fin field-effect transistor (FinFET) having a triple-structure that is in a first region on the substrate; and

a second FinFET having a double-gate structure that is in a second region on the substrate,

wherein logic transistors are disposed in the first region and input/output (I/O) transistors are disposed in the second region,

wherein a height of a first fin of the first FinFET relative to the substrate is greater than or equal to a height of a second fin of the second FinFET relative to the substrate.

15. The semiconductor device of claim 14, wherein a first dielectric film on a top surface of the first fin is thinner than a second dielectric film on a top surface of the second fin.

16. The semiconductor device of claim 15, wherein:

the first FinFET comprises a first gate electrode that surrounds a channel region of the first fin with the first dielectric film disposed between the first gate electrode and the first fin; and

the second FinFET comprises a second gate electrode that surrounds a channel region of the second fin with the second dielectric film disposed between the second gate electrode and the second fin,

wherein a height of a top surface of the first gate electrode is substantially the same as that of the second gate electrode relative to the substrate.

17. The semiconductor device of claim 15, wherein the second fin extends in a first direction,

wherein a vertical cross-section of the second fin, perpendicular to the first direction, has a rectangular shape or a trapezoidal shape in which a lower side is longer than an upper side.

18. The semiconductor device of claim 14, wherein:

the first FinFET comprises a first gate electrode on opposing side surfaces and a top surface of the first fin with a dielectric film disposed between the first gate electrode and the first fin, and

the second FinFET comprises a second gate electrode on opposing side surfaces of the second fin with a dielectric film disposed between the second gate electrode and the second fin and a capping insulating film on a top surface of the second fin.

19. A semiconductor device, comprising:

a substrate comprising a logic device region including logic transistors thereon and an input/output (I/O) device region including I/O transistors thereon adjacent the logic device region;

a first fin field-effect transistor (FinFET) on the logic device region, the first FinFET comprising a first semiconductor fin protruding from the substrate and a triple-gate structure comprising a first gate dielectric layer and a first gate electrode thereon; and

a second FinFET on the I/O device region, the second FinFET comprising a second semiconductor fin protruding from the substrate and a double-gate structure comprising a second gate dielectric layer and a second gate electrode thereon,

wherein the first and second gate dielectric layers have different thicknesses.

20. The device of claim 19, wherein:

a thickness of the second gate dielectric layer at a top portion of the second semiconductor fin is sufficient to prevent formation of a channel region at the top portion thereof during operation of the second FinFET; and

a thickness of the first gate dielectric layer at a top portion of the first semiconductor fin is sufficient to allow formation of a channel region at the top portion thereof during operation of the first FinFET.

21. The device of claim 20, wherein the second gate dielectric layer comprises:

a capping insulating film on the top portion of the second semiconductor fin; and

an outer dielectric film having a uniform thickness that extends on the capping insulating film and along opposing sidewalls of the second semiconductor fin,

wherein the outer dielectric film has a same thickness as the first gate dielectric layer.

22. The device of claim 21, wherein the capping insulating film and/or the outer dielectric film comprise an etch-stop film.

23. The device of claim 20, wherein the first and second gate electrodes comprise electrically isolated portions of a same conductive layer.

24. The device of claim 23, wherein the first and second gate electrodes have a substantially uniform thickness on sidewalls and on top surfaces of the respective first and second semiconductor fins.

25. The device of claim 19, wherein a top portion of the second semiconductor fin is free of the second gate electrode, and wherein a surface of the second gate dielectric layer opposite the top portion of the second semiconductor fin is coplanar with a surface of a second gate electrode.

26. The device of claim 19, wherein a height of the first semiconductor fin relative to a surface of the substrate is greater than or equal to a height of the second semiconductor fin relative to the surface of the substrate, and/or wherein a width of the second semiconductor fin is greater than or equal to a width of the first semiconductor fin.

27. The device of claim 19, further comprising:

a third FinFET on the logic device region, the third FinFET comprising a third semiconductor fin protruding from the substrate and a double-gate structure comprising a third gate dielectric layer and a third gate electrode thereon, wherein a thickness of the third gate dielectric layer is greater than that of the first gate dielectric layer.

28. The device of claim 19, further comprising:

respective gate spacers on the first and second semiconductor fins between the first and second gate electrodes thereon and respective source/drain regions at ends thereof,

wherein the respective source/drain regions comprise epitaxial structures that are larger than respective channel regions of the first and second semiconductor fins in at least one dimension.