Strained isolation regions

• US 9,564,488 B2
• Filed: 04/22/2014
• Issued: 02/07/2017
• Est. Priority Date: 06/07/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Mong-Song, Lee, Tze-Liang, Huang, Kuo-Tai, Chen, Chao-Cheng, Lien, Hao-Ming, Peng, Chih-Tang
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US14/258,832
• Publication Number:
  US 20140242776A1
• Time in Patent Office: 1,022 Days
• Field of Search: 438/294, 438/296, 438/427
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming an isolation trench in a substrate, the isolation trench having sidewalls and a bottom;

forming an isolation material in the isolation trench, the isolation material extending between and directly contacting the sidewalls of the isolation trench and being recessed below a surface of the substrate such that an upper portion of the sidewalls is exposed, the isolation material having a planar top surface, the planar top surface being recessed below the surface of the substrate at a first depth;

after the isolation material is recessed below the surface of the substrate, forming a transistor on the substrate, comprising;

when the upper portion of the sidewalls is exposed, forming a gate dielectric layer, and

forming a gate electrode layer over the gate dielectric layer, wherein after forming the transistor the planar top surface is recessed below the surface of the substrate at a second depth, the second depth being substantially the same as the first depth; and

after forming the transistor, forming a stress layer over the substrate and the isolation material.

2. The method of claim 1, wherein the forming the isolation material includes:

forming a layer of the isolation material over the substrate, the layer substantially filling the isolation trench; and

planarizing the substrate and the isolation material such that top surfaces of the isolation material and the substrate are coplanar.

3. The method of claim 1, wherein the stress layer comprises a tensile stress film.

4. The method of claim 1, wherein the stress layer comprises a compressive stress film.

5. The method of claim 1, wherein the stress layer covers the transistor.

6. The method of claim 1, wherein the isolation material is recessed from about 200 Å

to about 500 Å

below the surface of the substrate.

7. A method of forming a semiconductor device, the method comprising:

forming a trench in a substrate;

forming a dielectric layer in the trench;

recessing the dielectric layer in the trench, the recessing forming a recess with reference to a major surface of the substrate, an upper surface of the dielectric layer being planar, the upper surface having a depth below the major surface of the substrate;

after recessing the dielectric layer, forming a transistor on the substrate, the transistor comprising a gate dielectric layer and a source/drain region interposed between the gate dielectric layer and the trench, the gate dielectric layer being formed after a bottom of the recess is below the major surface of the substrate, a lowermost surface of the source/drain region being above the upper surface of the dielectric layer; and

forming a stress layer over the substrate and the dielectric layer in the recess, the stress layer contacting a sidewall of the substrate in the trench, the stress layer extending over the major surface of the substrate.

8. The method of claim 7, further comprising, prior to the recessing, planarizing the substrate and the dielectric layer thereby removing the dielectric layer from a top surface of the substrate such that the dielectric layer in the trench and the substrate are coplanar.

9. The method of claim 7, wherein the recessing is performed at least in part by a wet etch process.

10. The method of claim 9, wherein the wet etch process is a timed etch process.

11. The method of claim 7, wherein the stress layer comprises a tensile stress film.

12. The method of claim 7, wherein the stress layer comprises a compressive stress film.

13. The method of claim 7, wherein the stress layer covers the transistor.

14. The method of claim 7, wherein the recess has a depth from about 200 Å

to about 500 Å

.

15. A method of forming a semiconductor device, the method comprising:

forming a trench in a substrate, the substrate having a first major surface;

forming a first dielectric layer over the substrate, the first dielectric layer substantially filling the trench;

planarizing the substrate such that the first major surface of the substrate and a second major surface of the first dielectric layer are co-planar;

recessing the first dielectric layer in the trench from the first major surface of the substrate, the first dielectric layer having a planar surface extending from a first sidewall of the trench to a second sidewall of the trench, a first portion of the first sidewall and a second portion of the second sidewall being exposed, the planar surface having a first depth below the first major surface of the substrate;

when the first portion of the first sidewall and the second portion of the second sidewall are exposed, forming a transistor on the substrate, the transistor comprising a gate electrode layer and a S/D region, the gate electrode layer being formed after the planar surface of the first dielectric layer is below the first major surface of the substrate, the S/D region adjacent to the first portion of the first sidewall, the S/D region having a second depth below the first major surface of the substrate, wherein the first depth is lower than the second depth; and

after forming the transistor, forming a stress layer over the substrate and the first dielectric layer, the stress layer in direct contact with the planar surface of the first dielectric layer and one of the first sidewall and the second sidewall of the trench.

16. The method of claim 15, wherein the stress layer comprises a tensile stress film.

17. The method of claim 15, wherein the stress layer comprises a compressive stress film.

18. The method of claim 15, wherein the stress layer covers the transistor.

19. The method of claim 15, wherein the recessing recesses at least a portion of the first dielectric layer from about 200 Å

to about 500 Å

below the first major surface of the substrate.

20. The method of claim 15, wherein the trench has a depth from 2000 Å

to about 3000 Å

.